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EEE 333, ASU
Fall 2009, David R. Allee
Homework #2
Due 22 September 2009
The objective of this homework is to exercise your learning of VHDL syntax, basic module
definitions and modeling of combinational logic. You can try to use modelsim to simulate and
check your answers.
1.
Data Types: Chapter 2 in Ashenden’s book
1.1 Write constant declarations for the number of bits in a 32 bit word and for the number
pi(3.14159).
1.2 Given the type declaration
type
state
is
(off, standby, active1, active2)
what are the values of
state’pos(standby)
state’succ(active2)
state’leftof(off)
state’val(2)
state’pred(active1)
state’rightof(off)
1.3 For each of the following expressions, indicate whether they are syntactically correct, and
if so, determine the resulting value.
2*3+6/4
3 + 4
true
and
x
and not
y
or
z
B”101110”
sll
3
(B”100010”
sra
1.4 Write a counter model with a clock input
clk
of type
bit
, and an output
q
of type
integer
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 Fall '09
 Ferry

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