HW 3 - solution

HW 3 solution - current_state<=E2 elsif(IE2='0 and IE3='0 then current_state<=F end if when E2 => output<="111" if IE3='1 then

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EEE 333, ASU Fall 2009, David R. Allee Homework #3 1. VHDL Implementation library IEEE use IEEE_Std_logic_1164.all; entity FSM is port( clk,reset : in std_logic; F,IE2,IE3,PF : in std_logic; Stall : out std_logic; output : out std_logic_vector(2 downto 0)); end entity FSM; architecture behavior of FSM is type state is (F,E1,E2,E3,P); signal current_state:state; begin Moore:process(clk,reset) begin if reset='1' then current_state=F; elsif clk='1' and clk'event then case current_state is when F => output<="000"; if F='0' then stall <='1'; current_state <=F; else stall <='0'; current_state <=E1; end if; when E1 => output<="001"; stall <='0'; if (IE2='1' or IE3='1') then
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Unformatted text preview: current_state <=E2; elsif (IE2='0' and IE3='0') then current_state <=F; end if; when E2 => output<="111"; if IE3='1' then current_state <=E3; stall <='0'; elsif PF='1' then current_state <=P; stall <='1'; elsif IE3='0' then current_state <=F; stall <='0'; end if; when E3 => output<="101"; if PF='1' then current_state <=P; stall <='1'; else current_state <=F; stall <='0'; end if; when P => output<="100"; if PF='1' then current_state <=P; stall <='1'; else current_state <=F; stall <='1'; end if; when others => NULL; END CASE; END PROCESS; END architecture behavior; 2. State Transition Diagram...
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This note was uploaded on 10/28/2009 for the course EEE 333 taught by Professor Ferry during the Fall '09 term at ASU.

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HW 3 solution - current_state<=E2 elsif(IE2='0 and IE3='0 then current_state<=F end if when E2 => output<="111" if IE3='1 then

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