Lab 2 WRite Up

Lab 2 WRite Up - L ab#2 8-Bit ALU Nathan Chen Professor Allee E EE 333 TTh 1:30 October 1 2009 VHDL CODE-Name Nathan Chen Lab#2 VHDL Code-library

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Lab #2: 8-Bit ALU Nathan Chen Professor Allee
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EEE 333 TTh 1:30 October 1, 2009
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VHDL CODE ----------------------------------------------------------------------------- Name: Nathan Chen Lab #2 VHDL Code ----------------------------------------------------------------------------- library ieee; use ieee.numeric_std.all; use ieee.numeric_bit.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity alu_8_bit IS port(Aluin_a, Aluin_b : in std_logic_vector(7 downto 0); Aluin_c : in std_logic_vector(3 downto 0); Cin : in std_logic; Alu_out : out std_logic_vector(7 downto 0); Cout : out std_logic); end alu_8_bit; architecture behavior of alu_8_bit is begin process(Aluin_a,Aluin_b,Cin,Aluin_c) variable temp: std_logic_vector(8 downto 0); variable count: std_logic_vector(7 downto 0); begin case Aluin_c is when "0000" => temp := ('0'&Aluin_a) + ('0'&Aluin_b); when "0001" => temp := ('0'&Aluin_a) + ('0'&Aluin_b) + ("00000000"&Cin); when "0010" => temp := ('0'&Aluin_a) - ('0'&Aluin_b); when "0011" => temp := ('0'&Aluin_a) - ('0'&Aluin_b) - ("00000000"&Cin); when "0100" => temp := '0' & to_stdlogicvector (to_bitvector(Aluin_a) srl conv_integer (Aluin_b));
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This note was uploaded on 10/28/2009 for the course EEE 333 taught by Professor Ferry during the Fall '09 term at ASU.

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Lab 2 WRite Up - L ab#2 8-Bit ALU Nathan Chen Professor Allee E EE 333 TTh 1:30 October 1 2009 VHDL CODE-Name Nathan Chen Lab#2 VHDL Code-library

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