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Unformatted text preview: Lab #3: 12-bit SRAM with 128 Address Locations Nathan Chen Professor Allee EEE 333 TTh 1:30 October 27, 2009 Objective The point of lab #3 is to practice our VHDL coding, memory design and test schemes. We were to model a 12-bit Static Random Access Memory (SRAM) using VHDL coding and to create a test bench to simulate the unit and verify the 12-bit output of the SRAM by using 5 pattern memory tests. The architecture should be a state machine to test the design and should write one of five patterns to the entire memory array before reading from the entire memory array and checking that the test pattern is correct. Each pattern should be written and then read from as an entire array. Once all five pattern tests are completed, the machine should go to a PASS state and quit or show a FAIL state and output the failing test and then quit. Design and Test Procedure The design is split up into two VHDL files. The first file is used to implement the programming of the SRAM. If the write is enabled, then the SRAM will write an input onto the memory. Otherwise, the SRAM will read an output. Moving onto the test bench, 5 different tests were conducted to verify that SRAM will read an output....
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This note was uploaded on 10/28/2009 for the course EEE 333 taught by Professor Ferry during the Fall '09 term at ASU.
- Fall '09