sram1 - architecture abstract of SRAM is subtype...

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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity SRAM is generic (bits: integer := 12; -- # of bits per word words: integer := 128); -- # of words in the memory port (rd, wr, clk: in std_logic; addr: in integer range words-1 downto 0; dataIn: in std_logic_vector(bits-1 downto 0); dataOut: out std_logic_vector (bits-1 downto 0) ); end entity SRAM;
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Unformatted text preview: architecture abstract of SRAM is subtype ram_address is integer range words-1 downto 0; type ram_array is array (ram_address) of std_logic_vector(bits-1 downto 0); signal memory: ram_array; begin process(clk) begin if rising_edge(clk) then if wr = '1' then memory(addr) <= dataIn; elsif rd = '1' then dataOut <= memory(addr); end if; end if; end process; end architecture abstract;...
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