tb - library ieee; use ieee. std_logic_1164.all; use ieee.

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library ieee; use ieee. std_logic_1164.all; use ieee. std_logic_arith.all; use ieee. std_logic_unsigned.all; entity TB is generic ( bits: integer := 12; -- # of bits per word words: integer := 128; -- # of words in the memory all_1s: std_logic_vector := "111111111111"; all_0s: std_logic_vector := "000000000000"; zeros_1s: std_logic_vector:= "010101010101"; ones_0s: std_logic_vector := "101010101010" ); end entity TB; architecture test_sram of TB is signal rd, wr: std_logic; signal clk: std_logic := '0'; signal enable : std_logic; signal test_start, reset : std_logic; signal y : std_logic; signal failpattern : std_logic_vector (2 downto 0); signal addr: integer range 0 to words-1; signal dataIn: std_logic_vector(bits-1 downto 0); signal dataOut: std_logic_vector (bits-1 downto 0); component FSM is generic ( bits : integer := 12 ; --number of bits words : integer := 128);--number of words port( w, r, clk, enable, test_start, reset: in std_logic; addr : in integer range words-1 downto 0; dataIn :
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This note was uploaded on 10/28/2009 for the course EEE 333 taught by Professor Ferry during the Fall '09 term at ASU.

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tb - library ieee; use ieee. std_logic_1164.all; use ieee.

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