{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

chapter1 - Chapter 1 An Introduction to Microelectronic...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 2
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 4
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Chapter 1 An Introduction to Microelectronic Fabrication e electronics industry has grown rapidly in the past four decades. This growth has been driven by a revolution in microelectronics. In the early 19603, putting more than one transistor on a piece of semiconductor was considered cutting edge. Integrated circuits {ICs} containing tens of devices were unheard of. Digital computers were large, slow, and extremely costly. Bell Labs, which had invented the transistor a decade earlier, rejected the concept of ICs. They reasoned that to achieve a working circuit all of the devices must work. Therefore, to have a 50% probability of functionality for a 20-transistor circuit, the probability of device functionality must be (0.5)“) = 0.966, or 96.6%. This was considered to be ridiculously optimistic at the time, yet today integrated circuits are built with billions of transistors. Early transistors were made from germanium, but most circuits are now made on silicon sub- strates. We will therefore emphasize silicon in this book. The second most popular material for build- ing ICs is gallium arsenide (GaAs). Where appropriate, the book will discuss the processes required for GaAs ICs. Although GaAs has a higher electron mobility than silicon, it also has several severe limitations, including low hole mobility, less stability during thermal processing, a poor thermal oxide, high cost, and perhaps most importantly, much higher defect densities. Silicon has therefore become the material of choice for highly integrated circuits. More recently microelectronic fabrica- tion techniques have been used to build a variety of structures including thin film devices and circuits, micromagnetics, optical devices, and micromechanical structures. In some cases these structures have also been integrated into chips containing electronic circuitry. A popular nonelectronic applica- tion, nucroelectromechanieal systems (MEMS), will be introduced later in this book. To chart the progress of silicon microelectronics, it is easiest to follow one type of chip. Memory chips have had essentially the same function for many years, making this type of analysis meaningful. Furthermore, they are extremely regular and can be sold in large volumes, making tech- nology customization for the chip design economical. As a result. memory chips have the highest density of all ICs. Figure 1.1 shows the density of dynamic random access memories (DRAMs) as a function of time. The vertical axis is logarithmic. The density of these circuits increases by incre- ments of 4X. Each of these increments takes approximately three years. One of the most fundamental 3 4 1 An Introduction to Microelectronic Fabrication 1n"1 10‘ :10“ 1o3 E E 101’ E E 105 .3 5. 1n2 2 2 10‘ a -= .E E E —Iu =1. _'__. .,__, 1 197a 1988 1990 zooo 2010 Year at first production '13:. Figure 1.1 Memory and minimum feature sizes for dynamic random access memories as a function of time (data from lC knowledge and ITRS Roadmap. 2005 edition). 2 1:! i-' H changes in the fabrication process that allows this technology evolution is the minimum feature size that can be printed on the chip. Not only does this increase lC density, the shorter distances that elec- trons and holes have to travel improve the transistor speed. Part of the IC performance improvement comes from this increased transistor performance. and part of it comes from being able to pack the tran— sistors closer together, decreasing the parasitic capac— itance. The right—hand side of Figure 1.1 shows that le have progressed from 10 microns {am} (i tun = 10" cm] to 0.1 pint or 100 nm. For sake of reference. Figure 1.2 shows an electron micrograph of a silicon—based IC‘ along with a human hair. The vertical and horizontal lines are metal wires used to interconnect the transistors. The transistors themselves Figure 1.2 Scanning electron micrograph (SEM) of an IC circa mid-198m. The visible lines correspond to metal wires connecting the transistors. 1.1 Microelectronic Technologies: A Simple Example 5 are below the metal and are not visible in the micrograph. At this rate of progress, chips with 65-nm features will be common by the time you read this book. At first glance, these incredible densities and the associated design complexity would seem extremely daunting. This book, however, will focus on how these circuits are built rather than how they are designed or how the transistors operate. The fabrication process is similar no matter how many tran— sistors are on the chip. The first half of the book will cover the basic operations required to build an IC, Using mechanical construction as an analogy, these would include steps such as forging, cutting, bend- ing, drilling, and welding. These steps will be called unit processes in this text. If one knows how to do each of these steps for a certain material (e.g.. steel), and if the machines and material required are avail~ able, they could be used to make a ladder or a high pressure cylinder or a small ship. The required nnm~ her and order of the steps will clearly depend on what is being built, but the basic unit processes remain the same. Furthermore, once a sequence that produces a good ship has been worked out, other ships of similar design could probably be built with the same process. The design of the ship, that is, what goes where, is a separate task. The shipbuilder is handed a set of blueprints to which he or she must build. The collection and ordering of these unit processes for making a useful product will be called a technology. Part V of the book will cover some of the basic fabrication technologies. Whether the technology is used to make microprocessors, L'O controllers, or any other digital function is largely immaterial to the fabrication process. Even many analog designs can be built using a technology very similar to that used to build most digital circuits. An IC, then, starts with a need for some sort of elec- tronic device. A designer or group of designers translates the requirements into a circuit design: that is, how many transistors, resistors, and capacitors must be used, what values they must have, and how they must be interconnected. The designer must have some input from the fabricator. In the ship- building example, the blueprints must somehow reflect the limitation that the shipbuilder cannot put rivets over weld joints or use small rivets and expect them to hold under very high pressures. The builder must therefore give the designer a document that says what can and cannot be done. In micro- electronics this document is called the design rules or layout rules. They specify how small or large some features can be or how close two different features can be. If the design conforms to these rules, the chip can be built with the given technology. 1.1 Microelectronic Technologies: A Simple Example Instead of blueprints, the circuit designer hands the IC fabricator a set of photomasks. The photo- masks are a physical representation of the design that has been produced in accordance with the layout rules. As an example of this interface, assume that a need exists for an IC consisting of a sim- ple voltage divider as shown in Figure 1.3. The technology to build this design is shown in Figure 1.4. Silicon wafers will be used as the substrate since they are flat, reasonably inexpensive, and most IC processing equipment is set up to handle them. The production of these substrates will be discussed in Chapter 2. Since the wafer is at least somewhat conductive, an insulating layer must first be deposited to prevent leakage between adjacent resistors. Alternatively, a thermal oxide of silicon could be grown, since it is an excellent insulator. The thermal oxidation of silicon is covered in Chapter 4. Next a conducting layer is deposited that will be used for the resistors. Several techniques for depositing both insulating and conducting layers will be discussed in Chapters 12 through 14. This conducting layer must be divided up into individual resistors. This can be done by remov- ing portions of the conducting layer, leaving rectangles of the film that are isolated from each other. The resistor value is given by Rzpwfir onic Fabrication 1 An Introduction to Microelectr — — I -'—"I {1) Starling water {2) Brow oxide 1“] {3} Deposit resistor material (4} Patlem resistor material 'Illfl (Ii) Pattern insulator ”I B It (I (5} Deposit insulator (A) {3] (7} Deposit metal {8} Paltsrn metal Figure 1.3 A simple resistor voltage divider. At left Figure 1.5 The technology flow for fabricating the resistor IC shown in Figure 1.3. is a circuit representation: at right is a physical layout. The layers shown at right are resistor. contact, and low-resistance metal. material resistivity, L is the resistor length stor width, and t is the thickness ' ' by choosing the width—to- where p is the ' t chooses the film of the layer. The designer can length ratio, subject to the limits specified by th thickness and the material (and therefore p) to give the designer an appropriate range of resistivities d t are determined during the fabrica- without forcing him to resort to extreme geometries. Since p an across a wafer, the ratio pit is more often specified than p or t where the number of ' ately constant individually. This ratio is called the sheet resistance, [3,. It has units of (ND. squares is the ratio of the length to width of the resistor line. each resistor, must be transferred The resistor information from the design, namely L and W for from the photomask to the wafer. This is done using a process called photolithogmphy. The most this process, a photosensitive commonly used type of photolithography is optical lithography. In layer called photoresist is first spread on the wafer (Figure 1.5). Light shining through the mask exposes the resist in the regions of the wafer where some of the metal resistor layer must be removed. In these exposed regions, a photochemical reaction occurs in the resist that causes it to be easily dis- solved in a develOper solution. After the develop step, the photoresist remains only in the areas where a resistor is desired. The wafer is then immersed in an acid that dissolves the exposed metal layer but does not significantly attack the resist. When the etch is complete, the wafers are removed from the acid bath, rinsed. and the p hie process will be covered in hotoresist is removed. The photolithograp Chapters 7 through 9. Chapter 1 1 will cover etching. Although the resistors have now been formed, they sti lines must be brought to the edge of the chip, where they can tact to the external world. This latter operation, called packaging. will not be covered in this text. If the metal lines have to cross over the resistors, another insulating layer must be deposited. To make electrical contact to the resistors, one can open up holes in the insulating layer using the same photo- lithographic and etch processes we had used for patterning the resistors, although the composition of the acid bath may be different. Finally, the fabrication sequence can be completed by depositing a highly conductive metal layer, applying a th 11 need to be interconnected, and metal later be attached to metal wires for con- ird mask, and etching this metal interconnect layer. 1.2 Unit Processes and Technologies 1 m The technology consists of four layers: the lower "1 insulator, the resistor film, the upper insulator, and the [1]Starting waiorwithleyer {2} Coat with photoresist interconnect metal. Photolithography is used to selec— to be patterned tively remove some of these layers in certain regions, but any point on the wafer must be made of some sub— set of these layers in the same order that they were built up. Except for the edges of the patterns, the thickness m of these films is constant. The technology uses three photolithography steps, three etch steps, and four thin [3} [lake the resist to set its {4} Expose resist in! shining film deposition (including oxide growth) steps. A very dissollfliflfl properties “El“ through a photomask similar set of steps could be used to fabricate a capaciw tor. With only a few more steps, simple transistors can be built. Notice that the comparison with shipbuilding m H breaks down in one critical respect. The effort required t I to build the IC is independent of the number of resis- Developer Etshanh _ tors. The photomask might define one resistor or {5} Immerse exposed water [6} Etch the film . . . . in developer 1,000,000I resistors (assurmng a l.000,000—resrstor err- cuit could be useful). In fact, two different sets of pho- Figure 1.5 Steps required for a pattern transfer using tomasks, one that defines only a few resistors and one Optical lithOgraphy‘ that defines thousands of resistors, could be used inter- changeably with exactly the same technology and would require the same amount of work. This is because most of the unit processes described in this book operate in the whole wafer at the same time instead of one rivet at a time. 1.2 Unit Processes and Technologies Some of the basic steps used in building an IC have already been discussed: photolithography, thin film deposition. and etching. Unit processes for thin film deposition include the processes of sputter- ing and evaporation. These are physical processes in that they do not generally depend on a chemical reaction. Sputtering is done by using charged atoms of argon called ions (AF) to bombard a target containing the deposition material. The target erodes under this bombardment. and some of the mater- ial falls onto the wafers, coating them with a thin film of material. Evaporation involves heating the material to be deposited to a high temperature so that a vapor stream is created. The wafers are placed in this stream for coating. The third thin film deposition process that will be discussed is chemical vapor deposition. In this technique one or more gases are made to flow into a chamber that contain the wafers to be coated. In many cases the wafers are also heated. A chemical reaction occurs that leaves the desired solid product on the surface of the wafer. A resistor was chosen to simplify the first example. Most semiconductor devices require the for- mation of doped regions. For example, consider the n-channel MOSFET shown in Figure 1.6. Some familiar layers from the resistor example are recognizable: a blanket insulator and a patterned metal layer. One can also selectively dope the source and drain regions, putting together a technology to make the transistor. Dopants are either donors (n-type) or acceptors (p-type). For silicon, the most common n— type dopants are arsenic, phosphorus. and antimony. and the most common p-type dopant is boron. For gallium arsenide the most common n-type dopants are silicon, sulfur, and selenium, and the most com- mon p—type dopants are carbon, beryllium, and zinc. In early semiconductor technologies, impurities were introduced by exposing heated wafers to a dopant~containing gas. For example, a hydrogent‘ phosphine (HgmHaj mixture can be used to introduce phosphorus into silicon. The introduction of dopant using this technique and the subsequent movement of the impurities when the wafer is heated is l __——————# fl 1 An Introduction to Microelectronic Fabrication a -substratc Figure 1.5 Cross section of an MOS transistor showing gate. source. drain, and substrate electrodes. The “+" and “-” indicate very heavy and very light dopings, respectively. called difiusion. This type of dopant introduction method allows the impurities to diffuse deep into the wafer. As a result, it is not desirable for the small devices required in modern fabrication technologies. Ion implantation, which has replaced it, uses a beam of ionized atoms or molecules electrostatically accelerated toward the wafer. This method allows the process technologist to control the amount of impurity introduced (dose) and the depth of the impurity in the wafer (range). To limit the diffusion of impurities, a new class of processes have been developed that allow the rapid heating (to high tempera- tures) and cooling of the wafer. This type of process is called rapid thermal processing (RTP). A number of processes that allow the growth of thin layers of semiconductor on top of the wafer will be discussed. These processes are called epitaxial growth. They allow the production of patterned dopant regions below the surface of the wafer. The book will first discuss the more trad- itional techniques of growing silicon on silicon and gallium arsenide on gallium arsenide (homoepi- taxy). It will then cover more advanced techniques that allow the growth of extremely thin layers for the fabrication of advanced device structures. The unit processes can be assembled into functional process modules. These modules are designed to carry out specific tasks such as the electrical isolation of adjacent transistors, low resist- ance contacts to transistors, and multiple layers of high density interconnect. All of these areas have had dramatic advances over the past few years. Clear trade-offs exist among the various modules in terms of process complexity. circuit density, planarity, and performance. These modules and the basic transistor fabrication are assembled into technologies. Several of the most popular technologies that represent a reasonable cross section of the microelectronics industry will be reviewed. Finally, tech- niques required for high volume manufacturing of ICs will be discussed. 1.3 A Roadmap for the Course The various unit processes for fabrication are fairly independent. Each of the next 13 chapters will cover a different unit process. To keep the book to a manageable size, each process can be only briefly introduced. In many cases, the chapters themselves can be expanded into books. The material in the chapter will provide references that will allow you to further investigate each topic if you have an interest. The result of this approach is sometimes called a survey course. Figure 1.? shOWS a map of the course chapters. The order that your instructor chooses to follow is completely arbitrary as long as the necessary introductory material is covered. These chapters and sections are marked with a °. The chapters and sections marked with a + are additional material some- what beyond the basic processes needed to describe simple semiconductor technologies. 1.4 Summary 5 Figure 1.? A roadmap for the course indicating the relationships between the chapters. The last six chapters of the book are dedicated to semiconductor technologies. The basic unit processes discussed earlier are brought together to form ICs made from silicon CMOS, bipolar transistors, GaAs field effect transistors, thin film transistors, light-emitting diodes, lasers and micro— mechanical devices. These technology examples have been chosen because they are popular and because they are representative of many other common technologies. As you might infer from the previous discussion, the same unit processes could be used to fabricate flash memories. charge coupled devices [CCDs}, sensors, solar cells, and other microdevices. The only differences are the number, type, and sequence of the processes used to form the technology. You are encouraged to look into one of these other fabrication technologies after you complete the course to see some of the other ways that these unit processes are applied. 1.4 Summary Integrated circuits have developed with incredible levels of complexity, exceeding 8 billion transistors per chip. Transistor density, as measured by DRAMS, quadruples about every three years, as it has since 1968. This book will introduce the technologies used to fabricate the ICs. The building blocks of these technologies are the unit processes of photolithography, oxidation, diffusion, ion implant- ation, etching, thin film deposition, and epitaxial growth. The unit processes can be assembled in different order and number, depending on...
View Full Document

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern