Process details

Process details - The MOSIS Service...

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The MOSIS Service More than 50,000 designs in 25 years of operation  Processes - Schedule - Prices - Web Forms - Contacts - Site Map Home  --> Products  --> Fabrication  --> Vendors  --> TSMC  --> TSMC 0.18 Micron Process  General Information About MOSIS Products Processes Prices Support User Group Events Job Openings News Work with MOSIS Getting Started Design and Test Requests Run Status Project Status Test Data Docs and Forms Documents Forms/Agreements Web Forms Quick Reference New Users Experienced Users Purchasing Agents Design and Test Academic Institutions Export Program Submit A Project Search MOSIS Taiwan Semiconductor (TSMC) 0.18 Micron CL018/CR018 (CM018) Process 1. Process Description This CMOS process has 6 metal layers and 1 poly layer. The process is for 1.8 volt applications. A thick oxide layer can be used for 3.3 volt transistors. Designs for this process require Metal 6 in the pad stack. Flip chip bumping is available from MOSIS. Please send e-mail to support@mosis.com
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This note was uploaded on 10/30/2009 for the course EE 8337 taught by Professor Harjani during the Fall '04 term at Minnesota.

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Process details - The MOSIS Service...

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