RF Dev's8337_2008d

RF Dev's8337_2008d - RF Devices Circuit components MOSFETS...

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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 1 RF Devices ± Circuit components z MOSFETS Short channel effects, F T , Noise z Resistors z Capacitors z Varactors ± RLC Networks ± Matching networks ± Inductor models
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 2 Circuit Components ± MOSFETs z Short channel z FT z Noise ± Passive z Inductors z Resistors z Capacitors
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 3 Why CMOS ± Allows for integration with digital z Good idea? ± Exploit large capital investment in digital CMOS z Low cost ± Speed is not a problem z Currently F T are in the range of 30GHz for 0.25u z Claimed to double every three years z In the laboratory FTs of 300GHz have been demonstrated ± Low noise designs can be done in CMOS z Source degenerated LNA designs ± Multiple interconnect layers z 5 - 6 metal layers
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 4 Process F T s ± Larry Larson, IEEE Personal Communications, June 1998 100 GHz
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 5 MOS Devices ± Gate resistance ± Gate resistance z Affects frequency response z Adds noise Rg eff = 1 3 W L R
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 6 Double Strapping ± Double strapping reduces resistance substantially ± In general use multiple fingers Rg eff = 1 3 × 4 W L R B. Razavi et. al. “Impact of distributed gate resistance on the performance of MOS devices, TCAS I, Nov 94 E. Morifuji et. al. , “Future perspective of scaling down roadmap of RF CMOS, VLSI Circuits Symp, June 99
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 7 Multiple Fingers ± Further reduction in gate resistance Typically Wf 12μ ± Beyond this metal resistance and contact resistance become a problem z Recall contact resistant 1 ~10 Rg eff = κ 3 1 N f W f L f R
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 8 Example Technology Resistances ± TSMC 0.18u thick metal 21.3 18.6 13.8 9.09 4.63 10 11.3 10.7 Contact resistance ( Ω ) 1003 929 0.01 0.07 0.07 0.08 0.08 0.08 316 60 7.7 7.5 6.6 Sheet Rho ( Ω /sq) HR Poly NW M6 M5 M4 M3 M2 M1 PLY+ BLK N+ BLK Pol y P+ N+ Intel 0.13u Copper Process
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 9 Modern CMOS Devices ± Modern CMOS devices have very short channels (L < 100 nm) and thin oxides (e.g. 0.13u Î 3.2nm) z Thin oxides reduce drain transistor (DIBL) ± Due to lithographic limitations and lateral diffusion there is overlap between the gate and the source/drain junctions. z Cgd cannot be neglected in modern processes z E.g. ~ 50% of Cgs for 0.13u CMOS (min length device) N+ N+ P+ G SD NMOS P+ P+ N+ G PMOS n-well p-substrate L overlap Vdd
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 10 Modern CMOS Process ± Example: 45nm process ± Ref: www.chipworks.com , Sony CXD9797GB Emotion Engine Microprocessor & Graphics Synthesizer
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Analog Design Group, University of Minnesota (harjani@ece.umn.edu) 11 MOS Cross-Section ± Scanning electron microscope (P. Allen, Georgia tech www.semiconductorglossary.com/)
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This note was uploaded on 10/30/2009 for the course EE 8337 taught by Professor Harjani during the Fall '04 term at Minnesota.

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RF Dev's8337_2008d - RF Devices Circuit components MOSFETS...

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