ee203_hw6_solution

ee203_hw6_solution - EE203A Digital System Homework#6...

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Unformatted text preview: EE203A Digital System Homework #6 Verilog HDL 1. Design an 8-bit adder and verify the 8-bit adder with some arbitrary input test patterns. (5 points) a) Design a 1-bit half adder module by using gate primitive instances. b) Design a 1-bit full adder module by using one continuous assignment. c) Design an 8-bit ripple carry adder which has two 8-bit inputs(a, b) and one 9-bit output(c) by using modules designed in a) and b). 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Design problems (5 points) a) Design a one-bit 4:1 MUX. i) Use if-else statement. ii) Use case statement. b) Design an 8-level indicator which has a 3-bit input (level[2:0]) and an 8-bit output(light[7:0]). What is level indicator? Remind mid-exam. i) Use case statement. ii) Use for-loop and if-else statements. c) Design a combinational logic which has an 8-bit input and a 1-bit output. In the module, if the number of high(“1”) bit in the eight input bits is equal to or exceeds four, then the output is high. If not, the output is low. The simpler code, the better. Verify your design with some arbitrary input test patterns. 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