chap14 - 289 Chapter 14 Exercise 14.1 The design of the...

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Unformatted text preview: 289 Chapter 14 Exercise 14.1 The design of the 2-read/1-write register le can be implemented with registers with 2 tristate outputs (A and B ), as shown in Figure 14.1. We call these registers: RF Registers. Besides the two tristate outputs, they have one input din, a write enable input EWi, and two \enable output" inputs: EOA and EOB to control each of the register tristate outputs. The design of this component based on a conventional register and tristate bu ers is also shown. The interconnection of all the A outputs of the RF registers forms the RBUSA (read bus A). Similarly for the B outputs. All the RF register inputs are also interconnected, forming the write bus WBUS. The binary decoders are used to generate the control signals for writing and reading the register le. IN WBUS 8 din 8 din 8 din RF Reg. EW LD din REG. EW0 EOA0 EOB0 A 8 clock EW1 RF Reg 0 B 8 EW15 RF Reg 1 RBUS B RBUS A EOA1 EOB1 EOA15 EOB15 RF Reg 15 CLK EOA EOB A B EOB0 RB 4 Binary Dec EOB1 EW0 WR 4 Binary Dec EW1 RA 4 Binary Dec EOA0 EOA1 EW15 EOA15 EOB15 8 IN 4 4 4 WR RA RB A Register File B 8 8 Figure 14.1: 2-read/1-write register le 290 Exercise 14.2 Solutions Manual - Introduction to Digital Design - December 6, 1999 The correct equation for this exercise is T = C1 ((j ; i) mod 2n ) + C2 (a) computation sequence for READ/WRITE operations We use VHDL to describe the system operation. The READ/WRITE is executed at a position that is ready for access, pointed by the Current Access Pointer (P). This pointer stays static when no access is requested. Either READ or WRITE requests must remain asserted while the operation is in progress. After the operation is performed, an ACK signal is issued and the control block waits for the READ/WRITE request to be removed before another memory cycle can start. When the READ/WRITE input is activated, the given address (A) is compared with P and the shift is activated while P 6= A. The system interface is shown in Figure 14.2. m data_in n Address CLK Rd Wr data_out m SAM ACK Figure 14.2: SAM block diagram The VHDL description for SAM memory system using a circular shift register and a counter follows. -- VHDL code for SAM - Sequential Access Memory - Exercise 14.2 LIBRARY ieee USE ieee.std_logic_unsigned.all PACKAGE sam_pkg IS CONSTANT N: NATURAL := 4 -- number of CONSTANT M: NATURAL := 4 -- number of SUBTYPE word is BIT_VECTOR (M-1 DOWNTO TYPE mem_array IS ARRAY (2**N-1 DOWNTO SUBTYPE addressT IS NATURAL RANGE 0 TO END sam_pkg USE work.sam_pkg.ALL ENTITY sam IS PORT ( data_in: IN word address: IN addressT Rd,Wr: IN BIT CLK: IN BIT data_out: OUT word ack: OUT BIT) END sam address bits bits per word 0) 0) OF word 2**N-1 Solutions Manual - Introduction to Digital Design - December 6, 1999 ARCHITECTURE high_level OF sam IS SIGNAL shift, ready: BIT SIGNAL DATA: mem_array SIGNAL access_addr: addressT BEGIN -- This process controls the data portion of the memory. -- when the shift input is activated, the access pointer -- is moved to the required address, one position at a time. -- the ready signal indicates that the required position -- was reached. This is the behavioral description of a -- circular shift register. DATA_REG: PROCESS (CLK,shift,address,access_addr) VARIABLE same_adr: BIT BEGIN IF (CLK'event and (CLK='1') and (shift='1')) THEN -- shift the data one position IF (same_adr='0') THEN IF (access_addr=2**N-1) THEN access_addr<= 0 ELSE access_addr<= access_addr+1 END IF END IF END IF IF (access_addr /= address) THEN same_adr := '0' ELSE same_adr := '1' END IF ready <= same_adr END PROCESS data_out <= data(access_addr) -- This process controls the access to the data portion -- The read/write controls are monitored and the ack signal -- is activated to indicate that the operation was completed CTR: PROCESS (CLK,Rd,Wr,ready) BEGIN IF (Rd'event OR Wr'event OR ready'event) THEN IF (Rd='1' OR Wr='1') THEN IF (ready='0') THEN shift <='1' ELSE shift <='0' END IF ELSE ack <= '0' shift <= '0' END IF END IF IF (CLK'event and (CLK='1') ) THEN IF ((Wr='1') and (ready='1')) THEN data(address) <= data_in ack <= '1' after 2 ns ELSE IF ((Rd='1') and (ready='1')) THEN ack<='1' after 2 ns ELSE ack<='0' after 2 ns END IF END IF END IF END PROCESS END high_level 291 292 Solutions Manual - Introduction to Digital Design - December 6, 1999 A timing diagram of the system operation is shown in Figure 14.3. /sam/data_in /sam/address /sam/rd /sam/wr /sam/clk /sam/data_out /sam/ack /sam/shift /sam/ready /sam/data /sam/access_adr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 0000 1101 0000 0110 0000 1101 1101 4 0110 6 8 4 0 Entity:sam 500 1 us 1500 2 us 2500 Page 1 3 us Architecture:high_level Date: Tue Oct 19 15:31:12 1999 Figure 14.3: Timing (b) The data path that supports the computation described in the VHDL code is shown in Figure 14.4. The following table list the control points and conditions for the data path: Signal Description load data control signal - loads the data in into the current (accessible) position of the circular shift register. shift control signal - forces the circular register to shift the information while the current address (access addr) is di erent than the requested address. data in data input and output for the circular shift register. data out ready condition signal - when 1 indicates that the requested position in the circular shift register was reached. Solutions Manual - Introduction to Digital Design - December 6, 1999 data_in shift SHIFT 293 m data_in load_data CLK Circular Shift Reg. LOAD CNT CLK data_out m Binary Counter n access_addr A address n B data_out Compare A=B ready data_in m m m m m m m m m 0 0 1 m 0 1 m 0 1 m 0 1 m m Reg. Reg. Reg. Reg. 1 m 2 m m 3 Reg. shift CLK load_data data_out circular shift register (5 positions) Figure 14.4: Data section for SAM computation Exercise 14.3 (a) T= 2n ;1 X where p(d) is the probability of distance d. As distances are uniformly distributed, we get: p(d) = 21n Based on the previous equations we obtain: d=0 (dC1 + C2 )p(d) T= 2n ;1 n (dC1 + C2 ) 21n = 21n 2n C2 + C1 22 (2n ; 1) d=0 X (b) when the average time becomes: T = C2 + C1 (2 2 ; 1) n p(d) = 1 if d = 1 0 otherwise T= 2n ;1 ( (14.1) X d=0 (dC1 + C2 )p(d) = C1 + C2 294 Solutions Manual - Introduction to Digital Design - December 6, 1999 (c) Block access. Time to access a block of k words is kC1 + C2 (when assuming pipelined execution C2 is absorbed in intermediate steps). The average time to go from block position i to block at position j , and access k consecutive positions is given as: n; 2X1 T Block = (dC1 + (k ; 1)C1 + C2 )p(d) n = 21n 22 (2n ; 1)C1 + 2n ((k ; 1)C1 + C2 ) n; = (2 2 1) C1 + (k ; 1)C1 + C2 1 n; = k (2 2 1) C1 + (k ; 1)C1 + C2 d=0 Direct-access memory: address A = (Ar As ), where Ar = A=M is a random access and As = A mod M is a sequential address. (a) design of direct-access memory with 16K words (14-bit address). Each word has 8 bits. The random address selects one among 210 = 1K sequential memory blocks of M = 16 words. A block diagram of the circuit is shown in Figure 14.5. Each SAM module is designed as described in Exercise 14.2. All SAM modules receive the same address, read, clock, and data input signals. Depending on Ar , one of the modules are selected by the signal selm<i>. When a module is selected, a write or read cycle may be performed. When reading, all modules will start accessing the requested address position, but only the module that is selected will generate the acknowledgement signal (ACK) and the output data. When writing, only the selected module will search the correct address position and perform the storage of the data input. (b) average access time. The time to access a position from the direct-access memory will depend on the time to access the SAM. The access time for a SAM with 1K words is given as: T = C1 ((j ; i) mod 24 ) + C2 where i is the current address, j is the requested address, C1 and C2 are implementation-dependent constants. case (a) distance between addresses of consecutive accesses is uniformly distributed: 24 ;1 X T = (dC1 + C2 )p(d) where p(d) is the probability of distance d. As distances are uniformly distributed, we get: p(d) = 214 Based on the previous equations we obtain: ! 4 ;1 2X 1 = 1 24 C + C 24 (24 ; 1) T = (dC1 + C2) 24 24 2 1 2 d=0 d=0 Exercise 14.4 T = C2 + C1 (22 ; 1) 4 Solutions Manual - Introduction to Digital Design - December 6, 1999 As data_in Write selm0 Read Wrm0 4 addr 8 data in Rd Wr 8 295 16-word SAM M0 ack clock selm0 As data_in Read Wrm1 selm1 4 8 selm0 addr data in Rd Wr 16-word SAM M1 ack clock 8 8 data_out selm1 selm1 As data_in Read Wrm15 selm1023 4 8 addr data in Rd Wr selm0 8 16-word SAM M1023 ack clock Ar selm15 10 selm1 Binary decoder selm1023 A 14 4 10 As Ar selm1023 ACK implemented using tree or coincident decoding Figure 14.5: Direct-access Memory block diagram case (b) when the distance between addresses is given by the function: ( p(d) = 1 if d = 1 0 otherwise the average time becomes: 24 ;1 (14.2) T= case (c) X d=0 (dC1 + C2 )p(d) = C1 + C2 Block access. Time to access a block of k words is kC1 + C2 (when assuming pipelined execution C2 is absorbed in intermediate steps). The average time to go from block position i to block at position j , and access k consecutive positions is given as: T Block = 24 ;1 X # 1 24 (24 ; 1)C + 24 ((k ; 1)C + C ) = 24 2 1 1 2 d=0 " (dC1 + (k ; 1)C1 + C2 )p(d) 296 Solutions Manual - Introduction to Digital Design - December 6, 1999 4; = (2 2 1) C1 + (k ; 1)C1 + C2 " # 1 (24 ; 1) C + (k ; 1)C + C =k 1 1 2 2 Exercise 14.5 R3 <= R1 LP1 <= R2 RP1 <= R1 LP2 <= R3 RP2 <= R4 R4 <= P2 R2 <= R4 LP1 <= R2 RP1 <= R1 LP2 <= R2 RP2 <= R3 R2 <= P2 R1 <= P1 R1 <= P1 The datapath for this computation is shown in Figure 14.6. R1 R2 R3 R4 P1 P2 Figure 14.6: Datapath for Exercise 14.5 Exercise 14.6 R{1,2} <= X R6 <= R{1,2,3,4,5,7} R7 <= OP{src1, R6} R{3,4,5} <= R7 ----load load load load R1, R2 with X R6 with any register {1,2,3,4,5,7} R7 with the OP result R3, R4, or R5 with register R7 where src1 2 fR1 R2 R3 R4 R5 R7g and OP = fadd sub incl AND XORg. Exercise 14.7 A state diagram for the control subsystem is shown in Figure 14.7. (a) execution of the computation for X = 00101110 and Y = 11100010. state A B C 0/1 xxxxxxxx xxxxxxxx xxxxxxxx 2 11100010 00101110 xxxxxxxx 5 00010000 00101110 xxxxxxxx 6 00010000 00101111 xxxxxxxx 0 00010000 00101111 00111111 Solutions Manual - Introduction to Digital Design - December 6, 1999 S 0 S 1 B=X A=Y 2 A=A+B A(7)=1 5 B=B+1 6 C=A+B A(7)=0 3 A=A 4 A=A+1 297 Figure 14.7: State Diagram for System in Exercise 14.7 Observe that the value of A(7) tested in state 2, corresponds to the present value of the variable A (1110010), not the value that is going to be valid when the machine leaves state 2 (00010000). (b) The data section that is required by the system is shown in Figure 14.8. Y 8 X 8 selA 0 1 selB 0 1 ldA clk A(7) Reg A ldB clk 8 8 Reg B A B 2 Operator 8 OP ldC clk Reg C 8 OP={add,incrA,incrB,notA} Figure 14.8: Datapath for Exercise 14.7 (c) The state diagram that describes the control behavior and the control signals activation is shown in Figure 14.9. For convenience, we replace the s input by start. The implementation of the control circuit using a counter, multiplexer, a decoder, and gates is shown in Figure 14.10. The parallel load of the counter is de ned as: 8 > 0 if S0 or S6 < I = > 5 if S2 (14.3) : 6 if S4 A table that represents these values in a table is: 298 start’ 0 Solutions Manual - Introduction to Digital Design - December 6, 1999 start 1 ldA ldB 2 A(7)=0 3 4 OP={incrA} ldA OP={notA} OP={+} ldA ldA A(7)=1 5 ldB OP={incrB} 6 ldC OP={+} Figure 14.9: State diagram for the control section - Exercise 14.7 S2 S1’ S2’ S1 S1 S2 S3 S4 S5 S6 ldA start 1 not A(7) 1 0 1 0 d.c. 0 1 2 3 MUX 4 5 6 7 ldB ldC {+} cnt ld CK I2 I1 I0 counter Q2 Q1 Q0 S2 S6 S3 S4 S5 notA incrA incrB decoder 01234567 S0 ..... S7 Figure 14.10: Control network for Exercise 14.7 state code S0 000 S1 001 S2 010 S3 011 S4 100 S5 101 S6 110 S7 111 000 --101 --110 --000 --- I Minimal expressions are obtained with the following Kmaps: Solutions Manual - Introduction to Digital Design - December 6, 1999 299 s0 s2 I2 : 0--1 1--0 s0 s2 I1 : 0--0 1--0 s0 s2 I0 : 0--1 0--0 s1 s1 s1 I2 = s02 s1 + s2 s01 = s2 s1 I1 = s2 s01 I0 = s02 s1 The counter enable input is activated according to the expression: CNT = start:S0 + S1 + S2 A(7)0 + S3 + S5 and Another implementation of the control system using one FF per state approach is shown in Figure 14.11. start’ LD = CNT 0 CK S1 S2 S3 S4 S0 start S5 S6 S2 S6 ldA ldB ldC {+} CK CK A(7)’ S1 S2 S3 S4 S5 notA incrA incrB A(7) CK CK S3 S4 CK S5 CK S6 Figure 14.11: One- ip- op-per-state implementation of control system - Exercise 14.7 300 Exercise 14.8 Solutions Manual - Introduction to Digital Design - December 6, 1999 The data section of the system is shown in Figure 14.12. X 7 127 7 A A<B B A A=B B A A<B B Comparator newmax X ldmax CLK Comparator newmin Comparator 0 6 delimiter ldmin Reg. CLK Reg. end ecnt CLK LD Cnt Binary Counter 6 end CLK end Reg. 7 CLK end Reg. 7 CLK Reg. 6 MAX MIN COUNT Figure 14.12: Data Section of system for Exercise 14.8 A state diagram for the control part is shown in Figure 14.13. In this diagram we used the signal names presented in the data section block diagram. newmin and delimiter’/ ldmin,ecnt delimiter/end newmax and delimiter’/ ldmax, ecnt S0 /ldmax,ldmin,ecnt S1 newmax’ and newmin’ and delimiter’/ ecnt Figure 14.13: State Diagram for the Control Section - Exercise 14.8 The implementation of the control section using PLA is based on the following expressions: tation of the control section is shown in Figure 14.14. The one- ip- op-per-state implementation is given in Figure 14.15. ldmax = newmax:delimiter0 + S1 ldmin = newmin:delimiter0 + S1 end = delimiter:S0 ecnt = S0:delimiter0 + S1 nextstate = S0:delimiter = end where S0 corresponds to state = 0, and S1 corresponds to state = 1. The network for this implemen- Solutions Manual - Introduction to Digital Design - December 6, 1999 newmax newmin delimiter state 301 ldmax ldmin ecnt end D Q state Figure 14.14: Control section implementation using PLA - Exercise 14.8 delimiter D Q ecnt S0 CK end D Q newmax ldmax S1 CK newmin ldmin delimiter Figure 14.15: Control section implementation using one- -per-state approach - Exercise 14.8 302 Exercise 14.9 Solutions Manual - Introduction to Digital Design - December 6, 1999 The datapath for the system is shown in Figure 14.16. X C CK Reg, root**2 eps DIV DIV -1 ADD 1.0 A B CK MUX ABS A B MUL C CK Reg, ADD Compare A<B Reg, serror ROOT Figure 14.16: Datapath for the system in Exercise 14.9 The state diagram that describes the control section is shown in Figure 14.17. We consider that the system has a start input that indicates when another calculation must begin. start’ S0 start activates A,B,C S1 serror’ S2 activates B serror Figure 14.17: State Diagram for control section - Exercise 14.9 (a) implementation of the control section using D-type FFs. The states are encoded as: state y1 y0 S0 00 S1 01 S2 10 From these state codes we determine the binary transition table as follows: Input (start/serror) y1 y0 00 01 11 10 00 00,000 00,000 01,000 01,000 01 10,111 10,111 10,111 10,111 10 10,010 00,010 00,010 10,010 NS(Y1 Y0 ABC ) Solutions Manual - Introduction to Digital Design - December 6, 1999 These are minimal expressions for the next state and output signals: 303 Y1 Y0 A B = = = = y1 serror0 + y0 00 y1 y0start y0 = C y1 + y0 The gate network for the control section is shown in Figure 14.18. B Y1 D serror CK 1 Q y1 start y1’ CK Y0 D 0 Q y0 y0’ A,C Figure 14.18: Gate Network for control section - Exercise 14.9 (b) implementation of the control section using PLA. For this case we use the same expressions obtained for solution (a). The implementation is presented in Figure 14.19. y1 y0 serror start y0 D Q Y1 Y0 A,C B CK y1 D Q CK Figure 14.19: PLA implementation of control section - Exercise 14.9 304 Exercise 14.10 Solutions Manual - Introduction to Digital Design - December 6, 1999 (a) two counters and one shift register. With these components we have a better datapath for testing the bit value (using the shift register), counting the number of bits already tested in the input vector and counting the number of ones in the input vector (counters), when compared the the original data section. The data section of the system is presented in Figure 14.20(a). The X 8 load shift clk Shift Reg. clear 0 4 clk cnt ld Counter. 4 num_ones clear 0 clk cnt ld Counter. end (MSBit) Figure 14.20: Data section for Exercise 14.10a control sequence for the control section is described in VHDL as follows: PROCESS (clk) TYPE stateT IS (idle,loadval,count) VARIABLE state: stateT := idle BEGIN IF (clk'event and clk='1') THEN CASE state IS WHEN idle => load <= '0' shift <= '0' IF (start='0') THEN state := loadval ELSE state := idle END IF WHEN loadval => load <= '1' state := count WHEN count => load <= '0' shift <= '1' IF (end='1') THEN state := idle ELSE state := count END IF END CASE END IF END PROCESS The implementation of a microprogrammed control circuit is shown in Figure 14.21. Since the datapath is so especialized, the control circuit becomes very simple. There is no need for two instruction formats. The instruction format and the sequence of instructions in the microprogram is as follows: Solutions Manual - Introduction to Digital Design - December 6, 1999 address shift load cond branch address 0 0 0 01 0 1 0 1 00 { 2 1 0 10 2 3 0 0 00 0 305 on the data part conditions. The COND eld (cond) uses the codes: 00 for \no condition", 01 for start = 0, and 10 for end = 0. It would be better to use a simple sequential circuit to generate the control signals based +1 0 Mux 1 Adr Reg. ROM Ctr. Reg. shift load 0 start’ end’ d.c. 0 1 2 3 Branch address Mux cond Figure 14.21: Microcontroller network - Exercise 14.10a (b) Using one counter and a shift register. Di erently from part (a), this design needs the function provided by the original datapath. The shift register is used the same way as in part (a). The counter can be used to count the number of ones in the input X , or to control the number of bits already tested. In the rst case, we need to use the ALU to keep track of the number of bits tested. In the second approach, the ALU is used to test the end condition. We are going to use the rst solution. The data path for the system is shown in Figure 14.22 together with the state diagram for the control subsystem. The approach requires some modi cations on the instruction format presented in example 14.3 of the text: need to add one extra condition bit to test the bitval and end values. The conditions are: start - 00, bitval - 01, end - 10, and unconditional branch - 11. need to add the two control bits load and shift for the shift register and counter. The following is the micro-program for the unit: 306 Solutions Manual - Introduction to Digital Design - December 6, 1999 X 8 Data portion of example 14.3 load shift CLK start’ Shift Reg. idle bitval 0 cnt ld end (msbit) 4 start/ load, R7=0 test1 bitval=1/ R7=R7+1, shift bitval=0/ shift end=0 end=1/ Rout=R7 test2 CLK Counter 4 (a) data section (b) state diagram for control section behavior Figure 14.22: Datapath and control sequence for the system Exercise 14.10b Adr Mode ALU-op 0 1 2 3 4 5 6 7 8 0 1 0 1 0 0 1 0 1 FLD A sub=01 0 (start,0)=000 add=00 0 (bitval,0)=010 inc=11 7 nop x (end,0)=100 add=00 7 (unconditional,0)=110 BC 00 07 07 xx 07 ldRF 1 1 1 0 1 ldR sel s d r d load shift Note in out R in -0 0 -0 0 R0 0 1 -0 0 -1 0 R7 0 5 -0 0 -0 0 -0 0 -0 1 3 -1 0 -0 0 Rout R7 1 (c) just one counter. This situation forces the shifting of bits in the ALU. The counter is used to monitor the number of bits already scanned. The modi cations on the original program are: merge instructions at addresses 4 and 2 (remove R3 <= 1) change instruction at address 8 to test the end signal (coming from the counter) the instruction format must include a counter increment signal, which is activated in instruction at address 5. Exercise 14.11 (a) R0 maxfR0 R1 : : : R7g, R8 and R9 don't need to be preserved, fR1 R2 : : : R7g should be preserved. Considering that the values are already in the registers, the control signals S L1 : : : and L7 will have a value zero all the time. Since there is no \compare" operation, the comparison between two values x and y must be made by add/sub operation. When the operation x ; y is executed, the carry out bit (cy) is 0 only for the case y x. The RTL description of the computation is as follows: Solutions Manual - Introduction to Digital Design - December 6, 1999 R9 R8 R0 if R0 if . . . R0 if R0 <- R0 <- R0 <- R1 cy=0 R9 <- R2 cy=0 R9 R0 -- R8=0 R9 <- R1 R9 <- R2 307 <- R7 - R9 cy=0 R9 <- R7 <- R9 + R8 -- R0=R9 If the registers were mapped to an array, we would be able to index each register, and this way use the FOR ... LOOP structure. (b) micro-instructions (horizontal/ implicit addressing) We use a two-format instruction. The condition eld is de ned as: 000-add, 001-sub, 010-incl, 011-xor, 100-and. The instruction formats and the instruction sequence is shown in the next table. Since the values of S and L1 to L7 are always zero, we don't show these signals in the microcode. Since there is only one condition to be tested, basically, the (cy 0) eld could be eliminated. We kept the condition in the instruction to keep the format similar to the one shown in the text. addr Mode source Register OP destination register 0 E0 E1 E2 E3 E4 E5 E6 E7 E8 L0 L8 L9 1 (condition,value) address 0 0 1 0 0 0 0 0 0 0 0 --- 0 0 1 1 0 1 0 0 0 0 0 0 0 0 001 0 1 0 2 0 0 1 0 0 0 0 0 0 0 001 1 0 0 3 1 (cy,0) 5 4 0 0 1 0 0 0 0 0 0 0 --- 0 0 1 5 0 0 0 1 0 0 0 0 0 0 001 1 0 0 6 1 (cy,0) 8 7 0 0 0 1 0 0 0 0 0 0 --- 0 0 1 8 0 0 0 0 1 0 0 0 0 0 001 1 0 0 9 1 (cy,0) 11 10 0 0 0 0 1 0 0 0 0 0 --- 0 0 1 11 0 0 0 0 0 1 0 0 0 0 001 1 0 0 12 1 (cy,0) 14 13 0 0 0 0 0 1 0 0 0 0 --- 0 0 1 14 0 0 0 0 0 0 1 0 0 0 001 1 0 0 15 1 (cy,0) 17 16 0 0 0 0 0 0 1 0 0 0 --- 0 0 1 17 0 0 0 0 0 0 0 1 0 0 001 1 0 0 18 1 (cy,0) 20 19 0 0 0 0 0 0 0 1 0 0 --- 0 0 1 20 0 0 0 0 0 0 0 0 1 0 001 1 0 0 21 1 (cy,0) 23 22 0 0 0 0 0 0 0 0 1 0 --- 0 0 1 23 0 0 0 0 0 0 0 0 0 1 000 1 0 0 308 Exercise 14.12 Solutions Manual - Introduction to Digital Design - December 6, 1999 Bubblesort algorithm The block diagram for the datapath and the control circuit is shown in Figure 14.23. Shaded boxes represent registers. These are some of the components in the data section, and their function in the computation of the sorting algorithm: Register AD is used to store the previous address used to access the RAM. It is needed to perform the switch operation between two memory addresses. Registers A and B are used to store the information in the two positions being switched. Reg. A, in particular, stores one of the elements, while the comparison is made against another element in the RAM to detect if the element in position cnt1 is less than the element in position cnt1-1 (in this case the two elements are switched). The Up Counter starts from position 0, and scan the elements in the RAM, until it reaches the value of the Down Counter. This condition is indicated by the condition equal = 1. The Down Counter starts from the end of the list of elements, remains xed during a scan done with the up counter, and is decremented after each scan. It goes from the end to the top of the list of elements. The last value for this counter is 1. The state diagram of the control subsystem that operates on the proposed data path in order to implement the bubblesort algorithm is shown in Figure 14.24. The microprogram that implements the operations shown in the state diagram is stored in the ROM of a microcontroller, and is given in the following table. The explicit instruction format has both the branch (used when the condition tested is true) and the regular sequence address. The test conditions are represented by the codes: 00 - no branch, 01 - equal = 1, 10 - test = 1, 11 upcountone = 1. adr. ld1 cnt1 ld2 cnt2 ldad lda ea ldb eb ew s cond branch seq. 0 0 0 1 0 0 0 0 0 0 0 0 00 { 1 1 1 0 0 0 0 0 0 0 0 0 0 00 { 2 2 0 1 0 0 1 1 0 0 0 0 0 00 { 3 3 0 0 0 0 0 0 1 1 0 0 0 10 6 4 4 0 0 0 0 0 0 1 0 0 1 0 00 { 5 5 0 0 0 0 0 0 0 0 1 1 1 00 { 6 6 0 0 0 0 0 0 0 0 0 0 0 01 7 2 7 0 0 0 1 0 0 0 0 0 0 0 11 stop 1 Solutions Manual - Introduction to Digital Design - December 6, 1999 0 ld1 cnt1 clk n-1 ld2 cnt2 clk A Equals1 upcountone B A<B 8 8 309 up counter 8 AD 0 1 8 ADR dout 8 clk ldad 8 RAM din EN s lda ea Reg A ldb eb Reg B down counter equal Compare ew 8 compare test ROM adr. reg, 1 control signals branch sequence cond 0 equal test upcountone 0 0 1 2 3 Figure 14.23: Block diagram for Exercise 14.12 FIFO implementation. Based on the VHDL description of the FIFO operation, the data section must be able to store an input to any of the queue positions (following a given insertion order). This feature can be obtained with a broadcast of the input signal to all memory elements, and the control over the write enable signal of each element. Another required property is the ability to shift the information one position when a FIFO element is read. The proposed data section is shown in Figure 14.25. The shift signal is used in the read operation, to remove one element from the queue. The vector of control signals (wn;1 ::: w1 w0 ) is used to select one of the registers that will receive the input element during a write operation. The control section for the FIFO receives the Rd and Wr signals from the FIFO interface and generate the output signal Empty and Full, besides the internal control signals (wn;1 ::: w1 w0 ). The network for the control section is shown in Figure 14.26. It corresponds to a bidirectional shift register with parallel output and some additional control for the cases when the FIFO is empty or full. Some aspects of the design are important: Exercise 14.13 1. a reset signal was introduced to initialize the state of the FIFO control section, making w0 = 1. 2. instead of having a reference to the position of the last inserted element, we opted to have a 310 Solutions Manual - Introduction to Digital Design - December 6, 1999 /ld2 /ld1 /ldad,cnt1,lda test’/ test/ea,ldb upcountone’/cnt2 /ew,ea /ew,eb,s equal’/ upcountone equal/ Figure 14.24: State diagram for the control section - Exercise 14.12 reference to the next free position for writing (wi ). 3. when the FIFO is full (wn;1 ::: w1 w0 ) = (0 ::: 0 0), and Full = 1. 4. the empty condition is true when w0 = 1. Solutions Manual - Introduction to Digital Design - December 6, 1999 X 16 311 0 0 1 16 16 Reg n-1 LD 0 1 16 16 Reg 1 LD 0 1 16 16 Reg 0 LD Z shift clk w w1 w 0 n-1 Figure 14.25: Data section for the FIFO memory - Exercise 14.13 Wr w Full D Q Rd dir=1 -> right shift Ir shift dir Il n-1 FF clk reset Bidirectional Shift Register Rd Empty reset w0 Wr Full wn-1 wn-2 wn-3 w 1 w0 clk shift Empty Figure 14.26: Control section for the FIFO memory - Exercise 14.13 Exercise 14.14 LIFO implementation. Based on the VHDL description of the LIFO memory operation we should have a data path where we could read/write from/to di erent memory positions. The description keeps the elements on the position where they are written, and move the TOP of the stack after each PUSH or POP. However, a simpler implementation would be possible if the data input access only one memory element (TOP of the stack), and the data already stored in the memory were shifted to other positions in the stack. The data section to accomplish these tasks is shown in Figure 14.27. It is basically a bidirectional shift register where the input data is inserted in the rightmost position. The control section must generate the signals shift and dir to control the data section, based on the LIFO memory control inputs Rd and Wr. It also must generate the status signals for Full and Empty conditions. The network that implements the control section for the LIFO is shown in Figure 14.28. Since there is no pointer required to the address the TOP of the stack, a counter is used to monitor the number of elements in the stack. In order to have n elements in the stack, a k = dlog2 (n)e-bit counter is required. The shift and dir control signals are easily obtained from the Wrlifo and Rdlifo signals. A clear signal is necessary to reset the counter before the LIFO is 312 Solutions Manual - Introduction to Digital Design - December 6, 1999 X 16 0 0 1 16 16 Reg n-1 LD 0 1 16 16 Reg 1 LD 0 1 16 16 Reg 0 LD Z dir clk shift Figure 14.27: Data section for the LIFO memory - Exercise 14.14 used. clear Wrlifo 0 clk up ld k=log2(n) down up/down counter k Rdlifo 0 A B A=B n Wr A B A=B Wrlifo Rdlifo Rd dir shift compare compare Full Empty Figure 14.28: Control section for the LIFO memory - Exercise 14.14 ...
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This note was uploaded on 10/31/2009 for the course EE EE M16 taught by Professor Eshaghian,m.m. during the Fall '09 term at UCLA.

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