Unformatted text preview: 189 Chapter 10
Comparison of FA implementations (a) using a twolevel network (Fig. 10.3(a) of the textbook) the critical path for the circuit has 3 gates. The path connects the input xi (or yi or ci ) and output zi . The propagation delay of this path is obtained as:
Exercise 10.1 TpHL (xi ! zi) TpHL (xi ! zi) TpHL (xi ! zi) TpLH (xi ! zi) TpLH (xi ! zi) TpLH (xi ! zi) = = = = = = tpHL(NOT ) + tpLH (NAND ; 3) + tpHL (NAND ; 4) 0:05 + 0:017 2 + 0:07 + 0:038 1 + 0:12 + 0:051L 0:312 + 0:051L tpLH (NOT ) + tpHL (NAND ; 3) + tpLH (NAND ; 4) 0:02 + 0:038 2 + 0:09 + 0:039 1 + 0:10 + 0:037L 0:325 + 0:037L However, the delay of the path connecting the carry input to the carry output is also important for carry ripple adders. This path has a worst case delay: TpHL (ci ! ci+1 ) TpHL (ci ! ci+1 ) TpHL (ci ! ci+1 ) TpLH (ci ! ci+1 ) TpLH (ci ! ci+1 ) TpLH (ci ! ci+1 ) = = = = = = tpLH (NAND ; 2) + tpHL(NAND ; 3) 0:05 + 0:038 + 0:09 + 0:039L 0:18 + 0:039L tpHL(NAND ; 2) + tpLH (NAND ; 3) 0:08 + 0:027 + 0:07 + 0:038L 0:18 + 0:038L The number of equivalent gates is: gate type number of gates equivalent gates NOT 3 3 1=3 NAND3 5 5 2=10 NAND2 3 3 1=3 NAND4 1 1 2=2 Total 18 (b) using HA (Fig. 10.3(b) of the textbook) The critical path for this circuit has 3 gates: XOR2, AND2 and OR2. The path connects the input xi (or yi) and output ci+1 . The propagation delay of this path is obtained as: TpHL (xi ! ci+1 ) TpHL (xi ! ci+1 ) TpHL (xi ! ci+1 ) TpLH (xi ! ci+1 ) TpLH (xi ! ci+1 ) TpLH (xi ! ci+1 ) = = = = = = tpHL(XOR ; 2) + tpHL(AND ; 2) + tpHL(OR ; 2) 0:3 + 0:021 3 + 0:16 + 0:017 + 0:2 + 0:019L 0:74 + 0:019L tpLH (XOR ; 2) + tpLH (AND ; 2) + tpLH (OR ; 2) 0:3 + 0:036 3 + 0:15 + 0:037 + 0:12 + 0:037L 0:72 + 0:037L The number of equivalent gates is: 190 Solutions Manual  Introduction to Digital Design  June 3, 1999 gate type number of gates equivalent gates XOR2 2 2 3=6 AND2 2 2 2=4 OR2 1 1 2=2 Total 12 (c) using XOR and NAND gates (Fig. 10.3(c) of the textbook) As the NAND gates have smaller propagation delays than XOR gates, the critical path for this circuit is through the 2 XOR gates. The path connects the input xi (or yi) and output zi . Observe that when the rst XOR gate is connected to the input with higher load factor of the second XOR gate, the delay of the second XOR gate is reduced. So, two cases must be considered. The propagation delay of this path is obtained as: = tpLH (XOR ; 2) + tpLH (XOR ; 2) = max(0:3 + 0:036 3 + 0:16 + 0:036L 0:3 + 0:036 2:1 + 0:3 + 0:036L) = max(0:568 + 0:036L 0:6756 + 0:036L) = 0:68 + 0:036L = tpLH (XOR ; 2) + tpHL(XOR ; 2) = max(0:3 + 0:036 3 + 0:15 + 0:020L 0:3 + 0:036 2:1 + 0:3 + 0:021L) = max(0:558 + 0:02L 0:6756 + 0:021L) = 0:68 + 0:021L The carry output propagation delay is: TpLH (ci ! ci+1 ) = tpHL(NAND ; 2) + tpLH (NAND ; 2) TpLH (ci ! ci+1 ) = 0:08 + 0:027 + 0:05 + 0:038 L TpLH (ci ! ci+1 ) = 0:16 + 0:038L TpHL (ci ! ci+1 ) = tpLH (NAND ; 2) + tpHL(NAND ; 2) TpHL (ci ! ci+1 ) = 0:05 + 0:038 + 0:08 + 0:027L TpHL (ci ! ci+1 ) = 0:17 + 0:027L The number of equivalent gates is: gate type number of gates equivalent gates XOR2 2 2 3=6 AND2 3 3 1=3 Total 9 This last implementation is the one with the least number of gates. It also has less propagation delay for the carry than case (a).
Exercise 10.2 Analysis of a 4bit binary Carry Ripple Adder using the HA implementation with NANDs presented in Figure 10.3c of the textbook, each FA has 3 NAND2 and 2 XOR2 gates. Given the number of equivalent gates of the NAND2 (1) and XOR2 (3), the FA has a size of 9 equivalent gates, and the 4bit CRA has size 4 9 = 36 equivalent gates. The input load factors for the FA are: TpLH (xi ! zi ) TpLH (xi ! zi ) TpLH (xi ! zi ) TpLH (xi ! zi ) TpHL(xi ! zi ) TpHL(xi ! zi ) TpHL(xi ! zi ) TpHL(xi ! zi ) Solutions Manual  Introduction to Digital Design  June 3, 1999 191 Input load factor Input load xi 2.1 yi 3 ci 3 where we assume that the XOR input with highest load (2) is used for yi and ci . The worst case delay is given in the book (page 281) as: tp = tXOR + 2(n ; 1)tNAND + max(2tNAND tXOR ) Two NAND gates in series have a delay: tpLH (NAND ; NAND) = 0:08 + 0:027 + 0:05 + 0:038L = 0:16 + 0:038L tpHL(NAND ; NAND) = 0:05 + 0:038 + 0:08 + 0:027L = 0:17 + 0:027L and since cin is connected to the XOR input with L = 2, the XOR delay is: tpLH (XOR ; 2) = 0:16 + 0:036L tpHL (XOR ; 2) = 0:15 + 0:020L Since the XOR gate may complement or not its input any type of input transition may cause a desired output transition. The worst delay of the series of NAND gates is for LH transition. In this case, the critical path for each type of transition is: LH transition: XOR2 ! 4 two NAND2 ! XOR2 HL transition: XOR2 ! 5 two NAND2 and the delays are: TpLH (x0 ! z3 ) = 0:3 + 0:021 2:1 + 3 (0:168 + 0:027 3) + 0:16 + 0:036L TpLH (x0 ! z3 ) = 1:25 + 0:036L TpHL(x0 ! c4 ) = 0:3 + 0:021 2:1 + 3 (0:168 + 0:027 3) + 0:17 + 0:027L TpHL(x0 ! c4 ) = 1:26 + 0:027L Analysis of the 4bit Carry Lookahead Adder (Figure 10.5 from the textbook): In order to have a fair comparison, we replace the ANDOR network inside the CLG by a NANDNAND network. No decomposition into smaller gates is necessary since NANDs with 5 inputs are available on Table 4.1 of the textbook. The network size of the CLA when using NAND gates inside the CLG is: Gate type Number Eq. gate Size XOR2 8 3 24 AND2 4 2 8 NAND2 5 1 5 NAND3 4 2 8 NAND4 3 2 9 NAND5 2 4 8 OR4 1 3 3 AND4 1 3 3 Total 68 192 Solutions Manual  Introduction to Digital Design  June 3, 1999 For the delay we examine two possibilities: Option 1: tpLH (x0 ! c4 ) = tpLH (XOR2) + tpHL(NAND5) + tpLH (NAND5) tpLH (x0 ! c4 ) = 0:3 + 0:036 5:1 + 0:34 + 0:019 + 0:21 + 0:038L = 1:05 + 0:038L tpHL (x0 ! c4 ) = tpHL(XOR2) + tpLH (NAND5) + tpHL (NAND5) tpHL (x0 ! c4 ) = 0:3 + 0:021 5:1 + 0:21 + 0:038 + 0:34 + 0:019L = 1:00 + 0:019L Option 2: tpLH (x0 ! z3 ) = maxftpLH (XOR2) + tpHL(NAND4) + tpLH (NAND4) tpHL (XOR2) + tpLH (NAND4) + tpHL(NAND4)g + 0:16 + 0:036L tpLH (x0 ! z3 ) = maxf0:3 + 0:036 5:1 + 0:12 + 0:051 + 0:10 + 0:037 2 0:3 + 0:021 5:1 + 0:10 + 0:037 + 0:12 + 0:051 2g + 0:16 + 0:036L tpLH (x0 ! z3 ) = maxf0:66 0:77g + 0:16 + 0:036L tpLH (x0 ! z3 ) = 0:93 + 0:036L tpHL(x0 ! z3 ) = maxf: : :g + 0:15 + 0:020L tpHL(x0 ! z3 ) = 0:77 + 0:15 + 0:020L = 0:92 + 0:020L From these equations we determine the network delay taking the largest values for LH and HL transitions from both options: tpLH (x0 ! c4) = 1:05 + 0:038L tpHL(x0 ! c4) = 1:00 + 0:019L From these gures we conclude that the CLA adder uses more gates than the ripple carry adder but has a smaller propagation delay.
Exercise 10.3 The BCD to Excess3 converter using 4bit binary adder is shown in Figure 10.1. Exercise 10.4 BCD Addition When we add two BCD digits (0..9), considering a carryin bit, the range of values obtained is from 0 to 19. The output consists of a carry out and a digit coded in BCD also. s = (a + b + CIN ) mod 10 ( COUT = 1 if (a + b + CIN ) 10 0 if otherwise where s a and b are BCD digits. When the integers a and b are applied to the inputs of the binary adder, the output is: z = (a + b + CIN ) mod 24 ( 4 C0 = 1 if (a + b + CIN ) 2 0 if otherwise So, looking at the binary adder output and comparing to the expected output for the BCD adder, we must consider three cases: Solutions Manual  Introduction to Digital Design  June 3, 1999 193 BCD code 0011 not used cout Binary Adder cin 0 Excess3 Code Figure 10.1: BCD to Excess3 converter  Exercise 10.3 (i) C0 = 0 and z < 10: the output of the binary adder does not need correction (ii) 10 z 15 and C0 = 0: in this case we convert the sum as follows: As the operation is done with 4 bits, adding 6 is equivalent to subtracting 10. COUT = 1 (iii) C0 = 1: in this case z = (A + B + Cin ) ; 16 and we want s = (A + B + Cin ) mod 10. For this range of values we have (A + B + Cin ) mod 10 = (A + B + Cin ) ; 10, so we make: s = z mod 10 = (z ; 10) = (z + 6) mod 16 s = z +6 COUT = 1
Therefore, to obtain the BCD adder, the following operations must be performed to the binary adder output (z ): s= ( z if z 9 and C0 = 0 (z + 6) mod 16 if 10 z 15 or C0 = 1 COUT = ( 0 if z 9 and C0 = 0 1 if z 10 or C0 = 1 The condition z 10 or C0 = 1 is described by the switching expression: w = (z1 z3 + z2 z3 + C0)
The circuit is shown in Figure 10.2.
Exercise 10.5: Adder of decimal digits in Excess3 code. 194 Solutions Manual  Introduction to Digital Design  June 3, 1999 _ a _ b Binary Adder cin =0 0 0 Binary Adder 0 Cout _ s Figure 10.2: BCD adder (Exercise 10.4) Let a and b be the decimal digits to be added. The addition is described by: s = (a + b + Cin) mod 10 ( if (a + b + Cout = 1 otherwise Cin) 10 0
The relation between the Excess3 and the binary representation of a is: ar (E3 ) = ar (bin ) + 3
where ar (bin ) = ar (E3 ) = 3 X 3 X i=0 i=0 ai (bin )2i ai (E3 )2i and similarly for b and s. Consequently, the digit addition is described by the following expressions: (a) If (ar (E3 ) + br (E3 ) + Cin ) < 16) (that means (a + b + Cin ) 9), then sr (E3 ) = ar (E3 ) + br (E3 ) ; 3 + Cin
and (b) If (ar (E3 ) + br (E3 ) + Cin ) 16) then Cout = 0 sr (E3 ) = ar (E3 ) + br (E3 ) ; 3 + Cin ; 10 Solutions Manual  Introduction to Digital Design  June 3, 1999 195 and Cout = 1 Now consider the implementation. If we apply a and b in E3 code to a 4bit binary adder we get the sum z and the carryout bit (Co ) as: z = (ar (E3 ) + br (E3 ) + Cin) mod 16 Co = 1 if (ar (E3 ) + br (E3 ) + Cin ) 16 Comparing the expressions for (sr Cout ) and (z Co ) we get: ( sr (E3 ) = z ; 3 if Co = 0 z + 3 if Co = 1 Cout = Co and since z ; 3 = (z + 13) mod 16, we obtain the network of Figure 10.3, on page 195.
_ a 4 _ b 4 and Cout Binary Adder Cin 4 _ z Excess3 adder Binary Adder 4 _ s Figure 10.3: Excess3 adder  Exercise 10.5
Exercise 10.6 The connection between the decoder and the encoder implies: output of the adder is: w = (a b c) = (x + 2) mod 8 Considering x and y the integers represented by (x2 x1 x0 ) and (y2 y1 y0 ), respectively, the z = (w + y) mod 8 z = (x + y + 2) mod 8 and substituting w, we get: 196 Solutions Manual  Introduction to Digital Design  June 3, 1999 The switching functions can be obtained introducing the appropriate codes for variables x and y, and specifying the functions by means of tables or expressions. This process is straighforward. However, the obtained highlevel description indicates that the system can be implemented with two 3bit adders to add up x, y, and 2 in modulo 8. The value An equivalent network with fewer modules is shown in Figure 10.4.
x2 x1 x0 y2 y1 y0 Binary ADDER cin 0 010 Binary ADDER cin 0 z2 z1 z0 Figure 10.4: Exercise 10.6
Exercise 10.7 Input: A B 2 f0 1 2 3g and Cin 2 f0 1g Output: Z 2 f0 1 2 3g and Cout 2 f0 1g Function: Z = (A + B + Cin) mod 4 ( C = 1 if (A + B + Cin) 4
out 0 otherwise A function table is shown in Table 10.1. The Kmaps for the cases cin = 0 and cin = 1 are shown next: cin = 0 b0 b0 b0
0 1 1 0 1 0 0 1 1 0 0 1 0 1a 0 1 0 a1 Cout: 0 0 0 0 0 0 1 0 0 1 1 1 0 0a 0 1 1 a1 z1 : 0 0 1 1 0 1 0 1 1 0 1 0 1 1a 0 0 0 a1 z0 : b1 b1 b1 Solutions Manual  Introduction to Digital Design  June 3, 1999 197 i
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 C in a1 a0 b1 b0 C
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Inputs Outputs 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 out z1 z0
0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 10.1: Function table of a 2bit adder 198 Solutions Manual  Introduction to Digital Design  June 3, 1999 cin = 1
0 0 1 0 0 0 1 1 b0
1 1 1 1 0 1a 0 1 1 0 1 0 1 1 1 0 0 b0
0 0 1 1 1 0a 0 1 0 1 0 0 1 0 1 1 0 b0
0 1 1 0 1 0a 0 0 1 a1 Cout: a1 z1 : a1 z0 : b1 b1 b1 The following logic expressions are obtained from the Kmaps. Cout = (a1 b1 + a1 a0 b0 + a0 b1 b0 )c0in + (a1b1 + a0 b1 + a1 b0 + b1 b0 + a1 a0 )cin z1 = (b1 b00 a01 + a01 a00 b1 + a1 a0 b1b0 + a01 a0 b01b0 + a1a00 b01 + a1 b01 b00 )c0in +(a01 a00 b1 b00 + a1 a00 b01 b00 + a1 b1 b0 + a1 a0 b1 + a01 a0 b01 + a01 b01 b0 )cin z0 = (a00 b0 + a0 b00 )c0in + (a0 b0 + a00 b00 )cin
Using boolean algebra we reduce the expressions to: Cout = a1 b1 + a0 b1 b0 + a1a0 b0 + cin b1 b0 + cin a0 b1 + cin a1 a0 + cin a1 b0 z1 = a01 a00 b1 b00 + a01 a0 b01 b0 + a1 a0b1 b0 + a1 a00 b01 b00 + cin a01 b01 b0 + cin a01 a0 b01 + cin a1 a0 b1 + cin a1 b1 b0 + c0in a01 a00 b1 + c0in a01 b1 b00 + c0in a1 b01 b00 + c0in a1 a00 b01 z0 = cin a00 b00 + cina0 b0 + c0in a0 b00 + c0in a00 b0
From the equations, we count 26 NAND gates, with a maximum fanin of 12 inputs. We assume that NOT gates are used to obtain the complement of the input variables, so 5 NOT gates are also used in the network. The network has one level of NOT gates, and two levels of NAND gates. Internally, all NAND gates in the intermediate level are connected to only one input of the next level, all loads are 1. The loads of the input signals and their complements (generated by the NOT gates) are: Signal Load a1 11 a01 6 b1 11 b01 6 a0 11 6 a00 b0 11 b00 6 c 11 c0 6 Solutions Manual  Introduction to Digital Design  June 3, 1999 199 Design of a 6bit CLA adder using gates with a maximum of 4 inputs. The section that generates propagate and generate signals doesn't need gates with more than 2 inputs. The same for the last layer of XOR gates that generates the nal sum. The highest fanin is required by the gates inside the CLG module. The expressions for the CLG outputs are: c6 = g5 + p5 g4 + p5p4 g3 + p5 p4p3 g2 + p5p4p3 p2g1 + p5p4 p3p2 p1g0 + p5 p4 p3p2 p1 p0 c0 c5 = g4 + p4 g3 + p4p3 g2 + p4 p3p2 g1 + p4p3p2 p1g0 + p4p3 p2p1 p0c0 c4 = g3 + p3 g2 + p3p2 g1 + p3 p2 p1 g0 + p3p2 p1 p0c0 c3 = g2 + p2 g1 + p2p1 g0 + p2 p1 p0 c0 c2 = g1 + p1 g0 + p1p0 c0 c1 = g0 + p0 c0 P = p5p4 p3p2 p1 p0 G = g5 + p5 g4 + p5p4 g3 + p5 p4 p3 g2 + p5p4 p3 p2g1 + p5 p4 p3p2 p1g0
Exercise 10.8 From these expressions we observe that AND and OR gates with 5, 6 and 7 inputs are required. We decompose these gates into three gates. The implementation of the 6bit CLA is shown in Figure 10.5. From the Figure we count 66 gates distributed in 6 levels.
x5 y5 x4 y4 x3 y3 g3 p3 x2 y2 x1 y1 x0 y0 g5 p5 g4 p4 g2 p2 g1 p1 g0 p0 c0 p2 p3 c3 s2 c2 p1 p0 c0 c1 P G c6 p5 c5 s5 p4 c4 s3 s1 s0 s4 Figure 10.5: 6bit CLA using gates of at most 4 inputs  Exercise 10.8 Design of 64bit adders. a) a Ripple Carry Adder (RCA) using 4bit adder modules is shown in Figure 10.6. This implementation of a 64bit adder needs 16 adder modules (CLA4). The delay is: TCRA = C LA;xy;c4 + 14 C LA;c0;c4 + maxf C LA;c0;c4 C LA;c0;s3 g where C LA;xy;c4 is the delay to propagate the signal from input to the carry output of the 4bit CLA, and C LA;c0;c4 and C LA;c0;s3 are the delays from the input c0 to the carry out c4 and the sum output bit s3 , respectively.
Exercise 10.9 200
y _15 4 cout _ x 15 4 Solutions Manual  Introduction to Digital Design  June 3, 1999 y _ 1 4 _ x 1 4 y _ 0 4 _ x 0 4 cin 4bit adder 15 4 _15 z 4bit adder 1 4 _ z 4bit adder 0 4 _0 z 1 Figure 10.6: Carry Ripple Adder (CRA)  Exercise 10.9 Based on a NANDNAND implementation of the 4bit CLG that is part of the 4bit CLA we obtain:
C LA;xy;c4 = = = C LA;c0;s3 = = = C LA;c0;c4 = = = tLH (XOR ; 2) + tHL (NAND ; 5) + tLH (NAND ; 5) 0:30 + 0:036 5:1 + 0:34 + 0:019 1 + 0:21 + 0:038L 1:05 + 0:038L tLH (XOR ; 2) + tHL (NAND ; 4) + tLH (NAND ; 4) 0:3 + 0:036L + 0:21 + 0:038 1 + 0:34 + 0:019 2 0:93 + 0:036L tHL(NAND ; 5) + tLH (NAND ; 5) 0:21 + 0:038 1 + 0:34 + 0:019L 0:59 + 0:019L Based on the fact that the input load of c0 is 4, we obtain the delay of the CRA as: TCRA = 1:07 + 0:019 4 + 14(0:59 + 0:019 4) + 0:93 + 0:036L = 11:4 + 0:036L
b) a Carrylookahead Adder (CLA) using 4bit carrylookahead adder modules (CLA4) and 4bit carrylookahead generator modules (CLG4) is presented in Figure 10.7. Note that this design is an extension of the design showed in Figure 10.8 of the textbook. Observe from the Figure that 20 modules are necessary, 16 CLA modules and 4 CLG modules. The delay of this adder can be calculated considering the following module delays:
C LA;xy;PG C LG;pg;c4 C LG;c0;c3 = = = = = C LA;c0;s3 = = = C LA;xy;c4 = 1:07 + 0:019L C LA;c0;c4 = 0:59 + 0:019L tHL (NAND ; 4) + tLH (NAND ; 4) 0:21 + 0:038 1 + 0:34 + 0:019L 0:59 + 0:019L tLH (XOR ; 2) + tHL(NAND ; 4) + tLH (NAND ; 4) 0:3 + 0:036L + 0:21 + 0:038 1 + 0:34 + 0:019 2 0:93 + 0:036L Solutions Manual  Introduction to Digital Design  June 3, 1999 201 The load of the p, g, and c0 inputs of the CLG is 4. The total delay is: TCLA = C LA;xy;PG + C LG;pg;c4 + 2 C LG;c0;c4 + C LG;c0;c3 + C LA;c0;s3 = 1:07 + 0:019 4 + 0:59 + 0:019 4 + 2(0:59 + 0:019 4) + 0:59 + 0:019 4 +0:93 + 0:036L = 4:74 + 0:036L y15 x15 y14 x14 y13 x13 y12 x12 y11 x11 y10 x10 y 9 x 9 y 8 x 8 y 7 x 7 y 6 x 6 y 5 x 5 y 4 x 4 y 3 x 3 y 2 x 2 y 1 x 1 y 0 x 0 cin                4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c8 c4 _15 z _14 z CLG4 _13 z _12 z _11 z _10 z CLG4 _9 z _8 z _7 z _6 z CLG4 _5 z _4 z _3 z _2 z CLG4 _1 z _0 z c64 c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c8 c4 Figure 10.7: 64bit CLA with 1 level of CLGs  Exercise 10.9 Another approach is to use one more level of CLGs, this time to generate the carries of groups of 16 bits. This scheme is presented in Figure 10.8. The propagation delay of this case is: TCLAv2 = C LA;xy;PG + C LG;pg;pg + C LG;pg;c3 + C LG;c0;c3 + C LA;c0;s3 where C LG;pg;pg = C LA;c0;c4 = C LG;pg;c3 = C LG;c0;c3 = 0:59 + 0:019L. Thus TCLAv2 = 1:07 + 0:019 4 + 3(0:59 + 0:019 4) + 0:93 + 0:036L TCLAv2 = 4:07 + 0:036L which results in a faster implementation of the CLA, at the cost of one extra CLG4 module.
Exercise 10.10: considering radix r = 2 case (a)  two's complement, n = 7 bits C = 27 case (b)  one's complement, n = 8 bits C = 28 ; 1 case (c)  two's complement, n = 5 bits C = 25 case (d)  two's complement, n = 8 bits C = 28 Signed Integer  x Representation  xR Bit vector (in decimal) (in decimal) (a) 37 91 1011011 (b) 50 205 11001101 (c) 5 27 11011 (d) 9 9 00001001 202
c60 c56 c52 c48 c44 Solutions Manual  Introduction to Digital Design  June 3, 1999 y15 x15 y14 x14 y13 x13 y12 x12 y11 x11 y10 x10 y 9 x 9 y 8 x 8 y 7 x 7 y 6 x 6 y 5 x 5 y 4 x 4 y 3 x 3 y 2 x 2 y 1 x 1 y 0 x 0 cin                4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 CLA4 2 4 c40 c36 c32 c28 c24 c20 c16 c12 c8 c4 _15 z
2 _14 z
CLG4 _13 z _12 z c48
2 _11 z _10 z
CLG4 _9 z _8 z c32
2 _7 z _6 z
CLG4 _5 z _4 z c16
2 _3 z _2 z
CLG4 _1 z _0 z c60 c56 c52 c44 c40 c36
CLG4 c28 c24 c20 c12 c8 c4 c64 c48 c32 c16 Figure 10.8: 64bit CLA with 2 levels of CLGs  Exercise 10.9 We present now the calculations performed to obtain the numbers for the rst row (a). These numbers can be obtained in two di erent ways: using expressions or manipulating the vector of digits (or bits, if r = 2). Using the expression for x < 0, we know that: jxj = C ; xR = 27 ; xR = 37 So, xR = 27 ; 37 = 128 ; 37 = 91 . The vector of bits is easily obtained from this number in base 10. Another way is to manipulated the vector of digits. As we know, for two's complement number system, the representation of a number with a di erent sign is obtained complementing all digits with respect to (r ; 1) (the greatest digit) and adding one. First we get the representation for jxj: jxj = (37)10 = 0100101 note that the number was represented using n = 7 bits. 1011010 + 1 1011011 (10:1) Where 1011011 = (91)10 = xR .
Exercise 10.11: Fixedpoint number representation: (x6 x5 x4 :x3 x2 x1 x0 ) (a) Signandmagnitude: the most signi cant bit corresponds to the sign xmax = 011:1111 ! 2 2; 1 = 3:9375 4
6 6 xmin = 111:1111 ! ;(224; 1) = ;3:9375 Solutions Manual  Introduction to Digital Design  June 3, 1999 203 (b) Two's Complement xmax = 011:1111 ! 2 2; 1 = 3:9375 4
6 7 6 xmin = 100:0000 ! ;2 2+ 2 = ;4:0 4 (c) One's Complement xmax = 011:1111 ! 2 2; 1 = 3:9375 4
6 7 6 xmin = 100:0000 ! ;(2 ; 41) + 2 = ;3:9375 2 Exercise 10.12: For addition we use the following table: Kx Ky Kmx c0 x y z = x + y cout = c8 ovf zero sgn 00 1 0 01010011 00100111 01111010 0 0 0 0 00 1 0 01010011 01000001 10010100 0 1 0 1 00 1 0 10101010 10100000 01001010 1 1 0 0 00 1 0 10101010 11110001 10011011 1 0 0 1 00 1 0 10110110 00110011 11101001 0 0 0 1 00 1 0 10110110 01100111 00011101 1 0 0 0 For subtraction we use the table: Kx Ky Kmx c0 x y z = x ; y cout = c8 ovf zero sgn 01 1 1 01010011 00100111 00101100 1 0 0 0 01 1 1 01010011 01000001 00010010 1 0 0 0 01 1 1 10101010 10100000 00001010 1 0 0 0 01 1 1 10101010 11110001 10111001 0 0 0 1 01 1 1 10110110 00110011 10000011 1 0 0 1 01 1 1 10110110 01100111 01001111 1 1 0 0
Exercise 10.13: (a) to show that the addition in one's complement can be performed by two steps let us consider two numbers x and y represented by xR = x mod C and yR = y mod C , where C = 2n ; 1. We want to obtain sR = wR mod C , where wR = xR + yR is the result of the addition, represented by the vector wR = fwn wn;1 : : : w1 w0 ). The most signi cant bit of wR is the carry out bit of the n;bit addition performed with xR and yR . Since xR yR < C , wR < 2C . We must consider the following 3 cases: 1. If wR < C then wR mod C = wR and wn = 0 2. If wR = C then wR mod C = 0 and wn = 0 204 Solutions Manual  Introduction to Digital Design  June 3, 1999 3. If 2C > wR > C then wR mod C = wR ; C = wR ; 2n + 1 and wn = 1 Consequently, if wn = 0, the result is equal to wR , and if wn = 1 the result is obtained discarding wn (subtracting 2n ) and adding 1. Note that case (2) produces a result vector (1 1 : : : 1), which is correct since this is another representation of 0 in the one's complement system. (b) To verify that the operation of the adder with the carry output connected to the carryin is combinational we consider the following cases: there is a combination 00 or 11 for one particular bit position. In that case the carry chain is broken by this combination. No active loop. there is no combination 00 or 11, that means, all bit positions have the combination 01. In that case, there is an active loop. To have a stable result all carries have to be reset to zero before the operation starts. Figure 10.9 shows examples of both cases.
Some position with 00 or 11 011011010 100110101 ppppgpppp All positions with 01 or 10 cout 1 = cin 011001010 100110101 + 1 111111110 0 c 011001010 100110101 0 111101111 carry chain active loop spureous carry! carry bit carry chain no active loop Figure 10.9: Example of carry chains for One's complement adder  Exercise 10.13 (part b) sign bit). The algorithm for addition z = a + b in signandmagnitude representation is as follows: Input: a represented by (as am ), b represented by (bs bm ). Output: z represented by (zs zm ). Algorithm: IF as = bs THEN zm = am + bm zm = am ELSE IF (am bm ) THEN zm = am ; bm zs = as ELSE zm = bm ; am zs = bs
Exercise 10.14: Implementation of addition in Signandmagnitude with 8 bits (including the Solutions Manual  Introduction to Digital Design  June 3, 1999 205 (a) the design using a subtractor of magnitudes, one adder/subtractor, twomuxes and gates is shown in Figure 10.10. The di erence in sign between the operands is detected by the XOR gate, that controls the adder/subtractor. The magnitude subtractor is used to compare the operands, performing the operation (a ; b). The comparison result is obtained from the borrow output. When the borrow output is 1, a < b. Using the result of this comparison, the larger magnitude operand is routed to the rst input of the adder/subtractor, and the smaller one to the second input (subtraend). The output of the adder/subtractor corresponds to the magnitude part of the result. The sign must be selected, and it must be the sign of the number with the largest absolute value. This operation is accomplished by a multiplexer controlled by the borrow output of the magnitude subtractor, as shown in the Figure.
x sign(x) 8 sign(y) 7
0 y 8 7
0 bout bout =1 if a<b
a b bin Mux 1 1 Mux Mag. Subtractor sign(x)
0 1sub 0add Adder/subtractor sign(y)
1 Mux sign(x+y) x+y Figure 10.10: SM Adder  Exercise 10.14 (part a) (b) the design with conversion of the SM number to two's complement, operation in two's complement system, and conversion back to SM system is shown in Figure 10.11. The conversion from SM to two's complement is done as follows, considering x = (xn xn;1 : : : x1 x0 ) as the SM representation of an operand (xn is the sign) and z its 2's complement representation: ( z = (0 xn;1 :: :: :: x1 x0 ) + 1 if xn = 0 (1 x0n;1 x01 x00 ) if xn = 1 The conversion from two's complement to SM is done as follows: ( n 1 0 x = (0 zz 0;1 : :: :: : zz0 zz 0)) + 1) if zn = 0 (1 ( n;1 if zn = 1 1 0 The complementer and incrementer shown in the Figure are controlled by the sign bit of the numbers being converted. A better implementation would just complement one of the operands when the signs are di erent. This single complementation can be done by bitinvert and carryin forced to 1 in the adder, as shown in Figure 10.12.
Exercise 10.15: Consider the following table for the most signi cant bits of the operands an;1 and bn;1 and the sum bit sn;1 , during the addition of nbit two's complement operands a and b.: 206 Solutions Manual  Introduction to Digital Design  June 3, 1999 x sign(x) 0 8 7 sign(y) 0 y 8 7 Bit complementer 8 Incrementer Bit complementer 8 Incrementer Adder sign 8 7 Bit complementer 7 Incrementer 7 8 x+y 0 Figure 10.11: SM Adder  Exercise 10.14 (part b) 0 0 0 0 0 No 0 0 1 1 0 Yes 0 1 0 1 1 No 0 1 1 0 0 No 1 0 0 1 1 No 1 0 1 0 0 No 1 1 0 0 1 Yes 1 1 1 1 1 No From the table one can see that the over ow cases are related to the cases when cn cn;1 = 1. For the one's complement system the test doesn't work properly in the case of adding (;0) + (;2n;1 + 1), which corresponds to the addition of the vectors (111 : : : 11) and (100 : : : 00). If the addition is performed in two stages (no endaroundcarry), the rst stage will generate cn = 1 and cn;1 = 0, detecting an over ow condition that does not exist.
Exercise 10.16: an;1 bn;1 sn;1 cn cn;1 Ovf n < m, such that: The range extension of x = (xn;1 : : : x1 x0 ) is represented as z = (zm;1 : : : z1 z0 ), with ; zi = xn;1 for i = m; 11 :::::: 1n 0 xi for i = n ( To show the correctness of this implementation let us de ne: z = zR mod Cz x = xR mod Cx Solutions Manual  Introduction to Digital Design  June 3, 1999 207 x sign(x) 0 8 7 sign(y) 0 y 8 7 Bit complementer 8 dif Adder sign 8 7 Bit complementer 8 dif Bit complementer 7 Incrementer 7 8 x+y Figure 10.12: Another solution for SM Adder  Exercise 10.14 (part b) There are two possible cases: 1. if x 0 the most signi cant bit is zero, xn;1 = 0, and zR = xR , thus the algorithm is correct. 2. if x < 0 the following holds: zR = Cz ; jxj xR = Cx ; jxj
Consequently, zR = Cz ; Cx + xr . From the de nition of Cz and Cx we get: Cz ; Cx = 2m ; 2n and the value of the extended range zR should be: zR = 2m ; 2n + xR
From this last equation we get the following vector: (1 1 : : : 1 xn;1 : : : x0 ) with (m ; n) 1s to the left of vector x, which shows the correctness of the algorithm. A 4bit ALU for ADD and NAND operations is shown in Figure 10.13. A carryripple adder was implemented. By the use of a multiplexer, the output of the adder, or the NAND gate is selected as circuit output.
Exercise 10.17: 208
xi yi M Solutions Manual  Introduction to Digital Design  June 3, 1999 x3 y3 cin cout M x2 y2 x1 y1 x0 y0 cin M M M 1 Mux cout zi 0 ADD/NAND z3 z2 z1 z0 f=ADD/NAND Figure 10.13: 4bit ALU for ADD/NAND
Exercise 10.18: The analysis follows the inverse path of the description given on page 300 of the text. First, from the network, we obtain the switching expressions. Then, using the encoding given there, we obtain the highlevel description. As an intermediate step we could produce the following Table: 3 S G E E E E E E E Position i 210 output relation S x<y G x>y SS x<y GG x>y ESS x<y EGG x>y EES S x<y EEG G x>y E E E depends on cin x = y The G, E, and S conditions are mutually exclusive. Figure 10.14 shows the iterative structure to be designed. Each cell has one bit of each of the operands (ai and bi ), one carryin (CIN ), and one carryout (COUT ). These carries have three values: Equal, Greater, and Smaller. The comparator output is obtained from the carryout of the last cell. The highlevel description of the cell is:
Exercise 10.19: 8 > CIN if ai = bi < COUT = > GREATER if ((ai > bi ) and CIN = EQUAL) or (CIN = GREATER) : SMALLER if ((ai < bi) and CIN = EQUAL) or (CIN = SMALLER)
with the initial condition CIN = EQUAL (applied to the leftmost cell). Considering the following encoding: Solutions Manual  Introduction to Digital Design  June 3, 1999 209
a0 b0 a n1 b n1 a1 b1 carryin carryin 0 Iterative Bit Comparator Iterative Bit Comparator carryin 0 Figure 10.14: Iterative network to compare two numbers  Exercise 10.19 Condition Code EQUAL 00 SMALLER 01 GREATER 10 the implementation of each module is done as a combinational circuit that has the following switching function table: Observe that the code 11 is a don't care condition. Based on Kmaps for each COUT1 and COUT0 we get the expressions: These expressions are easily implemented by gate networks. The network that sorts two nonnegative numbers a and b is shown in Figure 10.15. The sorting order is such that z1 z0 . The output of the circuit for di erent conditions of a and b is shown in the next table.
Exercise 10.20: carryout ai biCIN1CIN0 COUT1 COUT0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00 01 10 { 01 01 10 { 10 01 10 { { { { { COUT1 = CIN1 + ai CIN00 COUT0 = CIN0 + biCIN10 carryout carryout Iterative Bit Comparator COMPARATOR OUTPUT 210
a b Solutions Manual  Introduction to Digital Design  June 3, 1999 A B Comparator A>B A=B A<B SEL s 0 MUX 1 s 0 MUX 1 z1 z0 Figure 10.15: Circuit to sort two nonnegative numbers Input condition SEL OUTPUT (z1 z0 ) a<b 0 (a b) a=b 0 (a b) a>b 1 (b a)
Exercise 10.21: A tree of 4bit comparators implementing a 32bit comparator is shown in Figure 10.16, where A(i) = (a4i+3 a4i+2 a4i+1 a4i ) and B (i) = (b4i+3 b4i+2 b4i+1 b4i ). The equality among inputs is implied when both G and S conditions are zeros. A (7) B (7) A (6) B (6) A (5) B (5) A (4) B (4) A (3) B (3) A (2) B (2) A (1) B (1) A (0) B (0) A B A B A B A B A B A B A B A B 4bit comparator G E S 4bit comparator G E S 4bit comparator G E S 4bit comparator G E S 4bit comparator G E S 4bit comparator G E S 4bit comparator G E S 4bit comparator G E S G signals S signals
A B G signals S signals
A B 4bit comparator G E S 4bit comparator G E S 00 00 A B cin inputs are zeroes for all modules 4bit comparator G E S Figure 10.16: 32bit comparator  Exercise 10.21
Exercise 10.22: The values of the outputs are shown in Figure 10.17. Solutions Manual  Introduction to Digital Design  June 3, 1999 211
0 1 2 DEMUX 0 0 1 0 1 1 0 1 0 1 2 MUX 3 4 5 6 7 2 10 2 g 1 3 4 5 6 7 0 0 1 0 0 0 0 0 10 0 10
d 0 (high) 1 PRIORITY ENCODER 2 3 4 5 6 7 a 2 b 1 0 c e ADDER f
carryin 1 0 1 0 carry_out 1 1 1 Figure 10.17: Exercise 10.22 Figure 10.18.
Exercise 10.23: The values of the outputs of each module in the array multiplier is shown in The implementation of the 8 4bit multiplier is shown in Figure 10.19. Exercise 10.24 212 x_bit sum_in y_bit x_bit y_bit x7 =1
1 x 6 =0 x5 =1 x 4 =1 x 3=0 x 2=0 x 1=1
1 x 0=1 y0
=1 c_out Half Adder
sum_out c_out Half Adder
sum_out 1 c_in 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 y1 =0 OR Module MH
1 x_bit sum_in y_bit 0 MH
0 0 0 MF
1 1 0 MF
0 1 0 0 MF
10 0 0 MF
10 0 0 MF
01 0 0 MF
01 0 MH
1 Solutions Manual  Introduction to Digital Design  June 3, 1999 Figure 10.18: Exercise 10.23 (a) MF
0 1 0 0 0 0 0 y 2 =0 0 c_out 0 MF
01 0 MF
1 1 1 0 MF
00 0 MF
1 0 1 0 MF
1 1 1 0 MF
0 1 0 MH
0 Full Adder
sum_out 1 c_in 1 1 1 1 y 3 =1 0 1 1 MF
1 0 1 0 MF
1 1 1 MF
0 1 1 MF
0 0 1 0 MF
1 0 1 MF
01 1 MF
01 0 MH
1 Module MF 1 1 1 1 1 y 4 =1 1 1 1 MF
0 0 1 MF
0 1 1 MF
0 1 0 MF
1 0 0 MF
0 0 0 MF
1 1 0 MF
1 1 0 MH
1 1 1 1 1 1 1 1 y5 =1 1 MF
0 0 MF
0 0 MF
1 0 MF
1 0 MF
1 0 MF
1 1 MF
1 1 MH
0 p13 p 12 p 11 p10 p9 p8 p7 (b) p6 p5 p4 p3 p2 p1 p0 Solutions Manual  Introduction to Digital Design  June 3, 1999 213 y7 y6 y5 y4 y3 y2 y1 y0 x0 y7 y6 y5 y4 y3 y2 y1 y0 x1 0
a3 cout a2 a1 s3 a0 s2 b3 s1 b2 s0 b1 b0 cin a3 cout a2 a1 s3 a0 s2 b3 s1 b2 s0 b1 b0 cin 4bit Binary adder 4bit Binary adder 0 y7 y6 y5 y4 y3 y2 y1 y0 x2 a3 cout a2 a1 s3 a0 s2 b3 s1 b2 s0 b1 4bit Binary adder b0 cin a3 cout a2 a1 s3 a0 s2 b3 s1 b2 s0 b1 4bit Binary adder b0 cin 0 y7 y6 y5 y4 y3 y2 y1 y0 x3 a3 cout a2 a1 s3 a0 s2 b3 s1 b2 s0 b1 4bit Binary adder b0 cin a3 cout a2 a1 s3 a0 s2 b3 s1 b2 s0 b1 4bit Binary adder b0 cin 0 z11 z10 z9 z8 z7 z6 z5 z4 z3 z2 z1 z0 Figure 10.19: 8 4bit multiplier  Exercise 10.24 ...
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 Fall '09
 ESHAGHIAN,M.M.
 Gate, Binarycoded decimal

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