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# chap9 - 163 Chapter 9 Exercise 9.1 a Implement a 10...

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Unformatted text preview: 163 Chapter 9 Exercise 9.1 a Implement a 10 output decimal decoder for 2-out-of-5 code using NAND gates. The 2-out-of-5 code represents decimal digits as shown in the following table: 0 1 2 3 4 5 6 7 8 9 i x4 x3 x2 x1 x0 00011 11000 10100 01100 10010 01010 00110 10001 01001 00101 Each output zi of the decoder is activated when the input has the 2-out-of-5 code that represents the value i in decimal and the enable input E = 1. The expressions for the outputs are: z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 = = = = = = = = = = x04 x03x02 x1 x0 E x4 x3x02 x01 x00 E x4 x03x2 x01 x00 E x04 x3x2 x01 x00 E x4 x03x02 x1 x00 E x04 x3x02 x1 x00 E x04 x03x2 x1 x00 E x4 x03x02 x01 x0 E x04 x3x02 x01 x0 E x04 x03x2 x01 x0 E Part of the gate network for the circuit is shown in Figure 9.1. x4 x3 x2 x1 x0 x4’ x3’ x2’ x1’ x0’ x4’ x3’ x2’ x1 x0 E x4 x3 x2’ x1’ x0’ E z0 z1 Figure 9.1: Network for Exercise 9.1 a 164 Solutions Manual - Introduction to Digital Design - March 22, 1999 b Implement a 10 output decimal decoder using NAND gates for a 4-bit Gray code. The code table is shown next. 0 1 2 3 4 5 6 7 8 9 i g3 g2 g1 g0 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 The expressions for the ten outputs z0 to z9 are: z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 = = = = = = = = = = 000 g2 g1 g0 E 00 g2 g1 g0 E 0 g2 g1 g0 E 00 g2 g1 g0 E 0 g2 g1 g0 E g2 g1 g0 E 00 g3 g2 g1 g0 E 0 00 g3 g2 g1 g0 E 0 g3 g0 E g3 g0 E The implementation, shown in Figure 9.2, consists of six 4-input NAND gates, two 5-input NAND gates, two 3-input NAND gates, and 14 NOT gates. c Implement a 10 output decimal decoder using NAND gates for a 2-4-2-1 code. The code table is shown next. 0 0000 1 0001 2 0010 3 0011 4 0100 5 1011 6 1100 7 1101 8 1110 9 1111 The switching expressions for the decoder outputs are: i c3 c2 c1c0 z0 = c03 c02 c01 c00 E Solutions Manual - Introduction to Digital Design - March 22, 1999 165 g2’ g1’ g0’ g2’ g1’ g0 z0 z1 g2’ g1 g0 g3 g2 g1 g0 g3’ g2’ g2’ g1 z2 g1’ g0’ g2 g0’ g1 g0’ g2 g1 g0 g3’ g2 g1’ g0 g3’ g2 g1’ g0 g3 g0’ g3 g0 z3 z4 z5 z6 z7 z8 z9 E Figure 9.2: Network for Exercise 9.1 b z1 z2 z3 z4 z5 z6 z7 z8 z9 = = = = = = = = = c03 c02 c01 c0 E c03 c02 c1 c00 E c03 c02 c1 c0 E c03 c2 c01 c00 E c3 c02 c1 c0 E c3 c2 c01 c00 E c3 c2 c01 c0 E c3 c2 c1 c00 E c3 c2 c1 c0 E Part of the gate network that implements these expressions is shown in Figure 9.3. 166 c3 c2 c1 c0 Solutions Manual - Introduction to Digital Design - March 22, 1999 c3’ c2’ c1’ c0’ c3’ c2’ c1’ c0’ E c3’ c2’ c1’ c0 E z0 z1 Figure 9.3: Gate network for Exercise 9.1 c Exercise 9.2: Implement a BCD decoder using an Excess-3 decoder, a 2-input binary decoder and a NOR gate. The relation between BCD code and the Excess-3 code is: x 0 1 2 3 4 5 6 7 8 9 10 11 12 z Ex-3 - - - 0 1 2 3 4 5 6 7 8 9 y BCD 0 1 2 3 4 5 6 7 8 9 - - where x is the radix-2 representation of the input vector and z and y are the indices of the outputs of the decoders with value 1. From the table we see that for x between 3 and 9, the output of the Excess-3 decoder can be relabeled to give some of the outputs of the BCD decoder. Since for x between 0 and 2, no output of the Excess-3 decoder has value 1, it is necessary to decode these values separately. It's possible to do this using a 2-input binary decoder that has as inputs the bits x1 and x0 the least signi cant bits and making the enable input active when x  3. The corresponding network is shown in Figure 9.4, on page 167. The 4-bit Odd Even parity functions have value 1 when the number of 1s in the input vector is odd even. The implementation of these functions using a 4-input decoder and OR gates is shown in Figure 9.5. The even parity is produced by output EP and the odd parity by output OP . Exercise 9.3 Exercise 9.4: For a coincident decoder using n = 12 and k = 4, we use r = n=k = 3 4-input decoders and 212 3-input AND gates. The circuit is shown in Figure 9.6. In the gure only some of the AND gates are shown, with the corresponding output numbers. In general, if we partition the input into groups of 4 bits, we get: u = 8x11 + 4x10 + 2x9 + x8 s = 8x7 + 4x6 + 2x5 + x4 t = 8x3 + 4x2 + 2x1 + x0 and the output zi = 1 if i = u28 + s24 + t. Solutions Manual - Introduction to Digital Design - March 22, 1999 167 x0 x1 x2 x3 0 1 2 3 0 4 1 Excess-3 dec 5 2 6 3 7 8 E9 y4 y5 y6 y7 y8 y9 BCD: (x3,x2,x1,x0) decoded outputs: yi E 0 Binary 0 1 dec 2 1 3 y0 y1 y2 y3 Figure 9.4: BCD decoder - Exercise 9.2 Exercise 9.5 Part a number of levels in the tree of decoders = 20=4 = 5 levels. the number of decoders in this tree = 1 + 16 + 162 + 163 + 164 = 69905 decoders. Part b using coincident decoding we need ve 4-input decoders to receive the 20 inputs. We would need 220 AND gates. Let us call x = x9 ; x8 ; x7 ; x6 ; x5 ; x4 ; x3 ; x2 ; x1 ; x0  the input vector of the 10-input decoder. The output vector will depend on the code to be generated. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 Exercise 9.6 x3 x2 x1 x0 3 2 Dec. 1 0 E 1 I1 I2 I4 I8 I7 I11 I13 I14 I0 I3 I5 I6 I9 I10 I12 I15 OP EP Figure 9.5: Parity functions - Exercise 9.3 168 Solutions Manual - Introduction to Digital Design - March 22, 1999 x11 x10 x9 x8 3210 E Decoder 15 14 210 x7 x6 x5 x4 3210 E Decoder 15 14 210 x3 x2 x1 x0 3210 E Decoder 15 14 210 E E E z4095 z4094 z31 z1 z0 Figure 9.6: Coincident decoder for Exercise 9.4 a For the 2-out-of-5 code consider the table presented in exercise 9.1 the expressions are: z4 z3 z2 z1 z0 = = = = = x1 + x2 + x4 + x7 E x1 + x3 + x5 + x8 E x2 + x3 + x6 + x9 E x0 + x4 + x5 + x6 E x0 + x7 + x8 + x9 E b For the 4-bit Gray code the output vector is z3 ; z2 ; z1 ; z0  see table in Exercise 9.1.. The expressions are: z3 z2 z1 z0 = = = = x8 + x9 E x4 + x5 + x6 + x7 + x8 + x9 E x2 + x3 + x4 + x5 E x1 + x2 + x5 + x6 + x9 E c For Excess-3 code the output vector is z3 ; z2 ; z1 ; z0 . The Excess-3 code is shown in the next table: 0 1 2 3 4 5 6 7 8 9 i z3 z2 z1z0 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Solutions Manual - Introduction to Digital Design - March 22, 1999 169 The expressions for the outputs are: z3 = x5 + x6 + x7 + x8 + x9 E z2 = x1 + x2 + x3 + x4 + x9 E z1 = x0 + x3 + x4 + x7 + x8 E z0 = x0 + x2 + x4 + x6 + x8 E The networks of gates are easily obtained from these expressions. Exercise 9.7 From the gure, we get the following expressions for the circuit outputs: 0 0 D = I8 + I9 0 = I8I9 0 0 0 0 0 0 C = I8 + I9 0 :I4 + I5 + I6 + I7 0 0 0 0 0 = I8 I9 :I4 + I5 + I6 + I7 0 0 0 0 0 B = I8I9 :I2 I4 I5 + I3 I4I5 + I6 + I7 0 0 0 0 0 = I8 I9 I6 + I7  + I9 I8 I7 I6 I5 I4 I3 + I2 0 0 0 0 0 0 A = I8 I9:I1 I2 I4I6 + I3 I4 I6 + I5 I6 + I7  + I90 0 0 0 0 0 = I9 + I9 I8 I7 + I9 I8 I7 I6 I5 + I9 I8 I7 I6 I5 I4 I3 + I9 I8 I7 I6 I5 I4 I3 I2 I1 0 From these expression we get the following table: 000000000 I9 I8 I7 I6 I5 I4 I3 I2 I1 D' C' B' A' Outputdecimal 1--------1001 9 01-------1000 8 001------0111 7 0001-----0110 6 00001----0101 5 000001---0100 4 0000001--0011 3 00000001-0010 2 0000000010001 1 0000000000000 0 Consequently, if Z = D0 ; C 0 ; B 0 ; A0  represents a decimal digit z in BCD, we get 0 i if Ii0 = z = 0 otherwise1 for some i 0 and Ij = 0 for all j i;  which corresponds to a priority encoder function. 170 Exercise 9.8 Solutions Manual - Introduction to Digital Design - March 22, 1999 : a From Figure 9.34 of the textbook we get the following table: BCD 7-segment display 0000 0000001 1001111 0001 0010 0010010 0011 0000110 0100 1001100 0100100 0101 0110 0100000 0111 0001111 1000 0000000 1001 0001100 The implementation of this code converter using a decoder and OR gates is shown in Figure 9.7. The implementation using a decoder and an encoder is not e cient, and for this reason it is not shown. Two 4-bit encoders or a large 7-bit encoder should be used, and since there is only a small set of 7-segment codes, many of the encoder inputs would not be used, or would require OR gates to combine two or more decoder outputs. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d b3 b2 b1 b0 abcdefg b0 b1 b2 b3 0 1 2 3 Binary decoder e f g E 1 Figure 9.7: Network of Exercise 9.8 a Solutions Manual - Introduction to Digital Design - March 22, 1999 171 b Four-bit binary to 4-bit Gray code. The function table is: binary Gray 0000 0000 0001 0001 0010 0011 0011 0010 0100 0110 0111 0101 0110 0101 0111 0100 1000 1100 1001 1101 1010 1111 1011 1110 1010 1100 1101 1011 1001 1110 1111 1000 Although the implementation by a gate network is quite simple, we show two di erent implementations in Figure 9.8. One uses a decoder and OR gates, and the other uses a decoder and encoder. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 g0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b3 b2 b1 b0 g3 g2 g1 g0 g1 b0 b1 b2 b3 0 1 2 3 b0 b1 b2 b3 0 1 2 3 Binary decoder Binary decoder Binary encoder g2 0 1 2 3 g0 g1 g2 g3 g3 E E 1 E 1 1 Figure 9.8: Binary to Gray-code converter - Exercise 9.8 b 172 Solutions Manual - Introduction to Digital Design - March 22, 1999 c BCD to 2-out-of-5 code converter. The function table of the system follows: BCD 2-out-of-5 0000 00011 11000 0001 0010 10100 01100 0011 0100 10010 01010 0101 0110 00110 10001 0111 1000 01001 00101 1001 Two implementations of this code converter, one using a decoder and OR gates, and another using a decoder and encoder are shown in Figure 9.9. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Binary 15 encoder 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E 31 1 b3 b2 b1 b0 c4 c3c2 c1 c0 c1 b0 b1 b2 b3 0 1 2 3 b0 b1 b2 b3 0 1 2 3 Binary decoder c2 Binary decoder c3 c4 E E 1 1 0 1 2 3 4 c0 c1 c2 c3 c4 0 Figure 9.9: Network of Exercise 9.8 c The implementation is shown in Figure 9.10, on page 173. The outputs of the decoder are labeled according to the Gray code and connected to the corresponding inputs of the encoder. Exercise 9.9: Exercise 9.10 A speci cation of the cyclic priority encoder is z = i if xi = 1 and xi+jmod 8 = 0 for j  c , i mod 8 Solutions Manual - Introduction to Digital Design - March 22, 1999 173 g2 g1 g0 0 1 2 Binary 1 decoder 3 4 5 0 6 E 7 2 0 1 2 2 Binary 3 Encoder 1 4 5 0 6 7E 1 b2 b1 b0 1 Figure 9.10: Code converter Binary-Gray, Exercise 9.9 where c is the value of the control input. In one implementation, a left 7-shifter is used to move the highest-priority input xc  to the highest input of the priority encoder w7 . The amount of shift is therefore 7 , c to the left this is obtained by complementing each bit of the binary representation of c. This produces wi+7,cmod 8 = xi , so that if xi is the highest-priority input, the output of the priority encoder would be i + 7 , c mod 8. Consequently, to obtain the correct result, the output of the encoder y has to be decremented by 7 , c mod 8. That is, z = y , 7 , c mod 8 = y + c + 1 mod 8 The corresponding network is shown in Figure 9.11a. To avoid the complementation of c, we can use a right shift of c instead of the left shift. This would put xc in w0 instead of w7 . Therefore, the connections between the output of the shifter and the input of the priority encoder have to be as shown in the Figure 9.11b. x1 x2 x3 x4 x5 x6 x7 x0 x1 x2 x3 x4 x5 x6 x7 -7 -6 Left -5 7-Shifter -4 w0 0 -3 1 -2 2 -1 3 0 4 1 5 2 6 w7 3 7 4 5 6 7 210 1 0 1 2 3 4 5 6 7 E 1 cin 0 Priority 1 Encoder 2 + z0 z1 z2 A A x0 x1 x2 x3 x4 x5 x6 x7 x0 x1 x2 x3 x4 x5 x6 c0 c1 c2 0 1 Right 2 7-Shifter 3 0 4 1 5 2 6 3 7 4 8 5 9 6 10 7 11 12 13 14 210 c2 c1 c0 1 0 1 2 3 4 5 6 7 E 0 Priority 1 Encoder 2 A (b) (a) Figure 9.11: Cyclic priority encoder - Exercise 9.10 174 Exercise 9.11 Solutions Manual - Introduction to Digital Design - March 22, 1999 Input: x 2 f0; 1; 2; 3; 4; 5; 6; 7g, represented in binary by the vector x = fx2 ; x1 ; x0 g; xi 2 f0; 1g. Output: y 2 f0; 1; 2; 3; 4; 5; 6; 7g, represented in binary by the vector y = fy2 ; y1 ; y0 g; yi 2 f0; 1g Function: y = 3x mod 8 The function table for the system is: x01234567 y03614725 The implementation of this system using a binary decoder and a binary encoder is shown in Figure 9.12. 0 1 Binary 2 1 decoder 3 4 5 0 6 E 7 2 0 1 2 2 Binary 3 Encoder 1 4 5 0 6 7E 1 x2 x1 x0 y2 y1 y0 1 Figure 9.12: Function y = 3x using decoder and encoder Exercise 9.12 The 64-input encoder network in Figure 9.35 of the textbook consists of two levels of modules. In the rst level there are eight encoders, each of them encoding part of the input vector x. Since there is only one input with value 1, the outputs of all encoder modules are 0 except the one corresponding to this xi = 1. Also, only the corresponding A has value 1. Naming wj the value of the 3-bit output of the encoder that has inputs xi, 8k  i  8k + 7, the output is described as: wj = i mod 8 0 and  if xi = 1 for j = bi=8c otherwise Aj =  1 0 if xi = 1 for j = bi=8c otherwise In the second level, there are three OR gates with eight inputs each which produce y2 ; y1 ; y0  and an eight-input encoder to encode the A outputs of the rst level encoders and produce y5 ; y4 ; y3 . The connection of the OR gates produces: 2 X j =0 yj 2j = ORw7 ; w6 ; :::; w0  = i mod 8 Solutions Manual - Introduction to Digital Design - March 22, 1999 175 since all w's except one are 0. Similarly, the output of the second-level encoder is 5 X j and, therefore, =3 yj 2j = bi=8c y= 5 X j and the network performs the encoding function. Exercise 9.13 The 256-input multiplexer has eight select inputs. Since each 4-input multiplexer has two select inputs, the tree has four levels. The number of multiplexer in each level is: rst level: 256 = 64 4 second level: 64 = 16 4 9:1 third level: 16 = 4 44 fourth level: 4 = 1 A total of 85 multiplexers distributed in four levels are required to implement a 256-input multiplexer. Exercise 9.14 =0 yj 2j = bi=8c  23 + i mod 8 = i The exercise asks for a multiplexer tree with r levels, and 2n inputs in the last level, with n = rk. That means, each multiplexer has k selection lines and 2k inputs. Figure 9.13 shows a block diagram of the rst and second level of the tree. We can see from the gure that from one level to the next, the number of inputs is multiplied by p = 2k the number of inputs of each individual multiplexer module. For r levels, the total number of inputs in the last level is pr = 2rk = 2n . p inputs Mux Mux Mux Mux p inputs Level 1 Level 2 2 Figure 9.13: Two levels of multiplexer tree The number of modules is: r j ,1 X =0 , pj = p0 + p1 + p2 + : : : + pr,1 = p , 11 p r 176 Exercise 9.15 Solutions Manual - Introduction to Digital Design - March 22, 1999 f a; b; c; d = oneset1; 3; 4; 9; 14; 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 abcd f a; b; c; d 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 a the implementation using 8-input multiplexer is presented in Figure 9.14. The expression can be manipulated as follows: f a; b; c; d = a0b0 c0 d + a0 b0cd + a0 bc0 d0 + ab0 c0 d + abcd0 + abcd f a; b; c; d = m0 a; b; cd + m1 a; b; cd + m2 a; b; cd0 + m4 a; b; cd + m7 a; b; cd0 + d d d d’ 0 d 0 0 1 0 1 2 3 4 5 6 7 MUX f(a,b,c,d) 210 abc Figure 9.14: Implementation for Exercise 9.15 a Solutions Manual - Introduction to Digital Design - March 22, 1999 177 b the implementation using 4-input multiplexer is presented in Figure 9.15. The expression for this implementation is: f a; b; c; d = m0 a; bc0 d + cd + m1a; bc0 d0 + m2a; bc0 d + m3 a; bcd + cd0  f a; b; c; d = m0 a; bd + m1 a; bc + d0 + m2 a; bc + d0 0 + m3a; bc d c d d c 0 1 2 3 1 0 MUX f(a,b,c,d) a b Figure 9.15: Network for Exercise 9.15 b Exercise 9.16 The implementation of an 8-input multiplexer using a 3-input binary decoder and NAND gates is shown in Figure 9.16. The selection lines s = s2 ; s1 ; s0  are decoded and used to make z = ij , such that j = s = s2 :22 + s1 :2 + s0 . i0 i1 s2 s1 s0 0 1 Binary 2 1 decoder 3 4 5 0 6 E 7 2 i2 i3 z i4 1 i5 i6 i7 Figure 9.16: Network for Exercise 9.16 178 Exercise 9.17 Solutions Manual - Introduction to Digital Design - March 22, 1999 Part a The speci cation of an n,bit simple shifter is given on page 265 of the textbook. A description of an 8-bit shifter is easily obtained from there. The block diagram of the circuit is shown in Figure 9.17. x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x -1 s d shift/no shift left/right SHIFTER E y7 y6 y5 y4 y3 y2 y1 y0 Figure 9.17: Block diagram of 8-bits shifter To generate each output, a 4-input multiplexer is used as shown in Figure 9.18. The selection inputs are de ned according to following table: c1 c0 Operation s dE 00 LEFT shift L 1 01 RIGHT shift R 1 10 NO SHIFT no shift - 1 11 DISABLED -0 Considering shift = L = 1 and no shift = R = 0 same convention used in page 266 of the textbook we obtain the following Kmaps: x i-1 0 1 2 3 1 c1 0 c0 yi MUX x i x i+1 0 Figure 9.18: Circuit for each output of the 8-bit simple shifter E s c1 111 1001  1 c0 E s 1001  1 0 1 1 d d Solutions Manual - Introduction to Digital Design - March 22, 1999 179 that correspond to the following expressions: c1 = E 0 + s0 c0 = sd + E 0 Part b An 8-bit bidirectional 3-shifter is speci ed as: Inputs: x = x10 ; x9 ; x8 ; x7 ; : : : ; x0 ; x,1 ; x,2 ; x,3, with xi 2 f0; 1g. s 2 f0; 1; 2; 3g Function: d 2 fL; Rg E 2 f0; 1g Output: y = y7 ; y6 ; : : : ; y1 ; y0 , with yj 2 f0; 1g. 8 yi = :0 xi,s if d = L and E = 1 xi+s if d = R and E = 1 otherwise 9:2 Let us assume that L = 1 and R = 0. Each output is generated by an 8-input multiplexer as shown in Figure 9.19. The table for the control inputs c2 c1 c0 is: x i-3 x i-2 x i-1 x i x i+1 x i+2 x i+3 0 0 1 2 3 4 MUX 5 6 7 210 y i c2 c1 c0 Figure 9.19: Circuit for each output of the 8-bit bidirectional shifter Eds c2 c1 c0 000 111 001 111 002 111 003 111 010 111 011 111 012 111 013 111 100 011 101 100 102 101 103 110 110 011 111 010 112 001 113 000 The values on the table are mapped into the following Kmaps, considering that s is represented in binary code: 180 Solutions Manual - Introduction to Digital Design - March 22, 1999 s0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 E c2 d c1 E s1 11 11 11 1 0  s0 1 1 11 00  10 s0 d c0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 E d s1 s1 The switching expressions are: c2 = E 0 + s1d0 + s0 d0 c1 = E 0 + ds01 + Es1 s0 + s01 s00 c0 = E 0 + s00 The module is obtained by renaming inputs and outputs of the shift register. For the right 3-shifter we have the speci cation: Inputs: x = xn+2 ; xn+1 ; xn ; xn,1; : : : ; x1 ; x0, with xi 2 f0; 1g s 2 f0; 1; 2; 3g E 2 f0; 1g Output: y = yn,1 ; yn,2 ; : : : ; y1 ; y0 , yi 2 f0; 1g Function: Exercise 9.18 if E = 1 yj = xj +s otherwise 0 And we would like to have a left 3-shifter, which is speci ed as: Inputs: w = wn,1; wn,2 ; : : : ; w1 ; w0 ; w,1 ; w,2 ; w,3 , with wi 2 f0; 1g s 2 f0; 1; 2; 3g E 2 f0; 1g Output: z = zn,1 ; zn,2 ; : : : ; z1 ; z0 , zi 2 f0; 1g Function:  9:3 zi = wi,s if E = 1 0 otherwise The mapping of the inputs is with k = n , 1 , i. Renaming the output also, we have  9:4 xi = wk yj = zt with t = n , 1 , j . Replacing these values on Equation 9.3 we obtain: zt = xn,1,t+s = wn,1,n,1,t+s = wt,s if E = 1 0 otherwise  9:5 Solutions Manual - Introduction to Digital Design - March 22, 1999 181 that corresponds to a 3-left shifter. A n-bit p-shifter has n + 2p input bits and n output bits. It can shift right or left direction input d and the distance of shifting can vary from 0 to p. The implementation of a 32-bit 3-shifter using four 8-bit 3-shifters is presented in Figure 9.20. The circuit on the top is a 32-bit 3-shifter that shifts to the left only. The circuit on the bottom of the gure is a bi-directional 32-bit 3-shifter. The input of the circuit was named i31 to i0 , and the output z31 to z0 . Exercise 9.19 i to i 31 24 i to i 23 16 i to i 15 8 i to i 7 0 shift inputs LEFT distance from 0 to 3 3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 d s 8-bit 3-shifter 3 d s 8-bit 3-shifter 3 d s 8-bit 3-shifter 3 d s 8-bit 3-shifter z to z 31 24 z to z 23 16 z to z 15 8 z to z 7 0 LEFT 32-bit 3-shifter i to i 31 24 i to i 23 16 i to i 15 8 i to i 7 0 shift inputs shift inputs 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 LEFT/RIGHT distance from 0 to 3 3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 d s 8-bit 3-shifter 3 d s 8-bit 3-shifter 3 d s 8-bit 3-shifter 3 d s 8-bit 3-shifter z to z 31 24 z to z 23 16 z to z 15 8 z to z 7 0 Bi-directional 32-bit 3-shifter Figure 9.20: Exercise 9.19 Exercise 9.20 Calling the output of stage 1 w1 and of stage 2 w2 then: w1j =  xj if s0 = 0 xj+1mod8 if s0 = 1 which indicates that this stage rotates 0 or 1 position left depending on the value of s0 . Similarly, w2j = Finally,  w 1j if s1 = 0 w1j +2mod8 if s1 = 1 182 Solutions Manual - Introduction to Digital Design - March 22, 1999 yj =  w 2j if s2 = 0 w2j+4mod8 if s2 = 1 and this corresponds to rotating 0 or 4 positions. Consequently, the module rotates left s = 4s2 + 2s1 + s0 positions with 0  s  7. For example, if the input vector is x7 ; x6 ; :::; x0  = 11010110 the output vector, for a rotation of 2 to the left is: 01011011. Design of Part a 12-bit right 3-shifter using 4-bit right shifter modules. The network is shown in Figure 9.21. Exercise 9.21 x14 x13 x12 x11 x10 x 9 x 8 x7 x6 x5 x4 x3 x2 x1 x0 dist 65 43210 right 3-shifter 3210 E dist 65 43210 right 3-shifter 3210 E dist 65 43210 right 3-shifter 3210 E d E Figure 9.21: 12-bit right 3-shifter Part b using k-bit right p-shifter modules we may implement a larger n-bit right p-shifter using: M = dne k modules of k-bit right p-shifter. The input vector of the n-bit shifter is: x = xn+p,1 ; xn+p,2 ; :::; xn,1 ; xn,2 ; :::; x1 ; x0  Each k-bit shifter module i receives the vector: xi = xik+p,1 ; :::; xik+1 ; xik  The enable and distance control lines of all shifters are connected together to from the control lines of the larger shifter. Exercise 9.22 Considering the network formed by the decoder and the multiplexer we have that z= 1 0  if w; d; e = f; g; h otherwise 9:6 where w is the output of the rst multiplexer. An expression for this output is: w = a0 b0c + bc0 + abc = ab + bc0 + a0 b0 c Solutions Manual - Introduction to Digital Design - March 22, 1999 183 a b b c’ a’ b’ c w f d g e h z Figure 9.22: Network for Exercise 9.22 The gate network that implements the network in Figure 9.38 of the textbook is shown in Figure 9.22. The equality comparator that generates z is implemented using XOR and NOR gates as proposed in the hint. The gate network to generate w is implemented with AND and OR gates. Exercise 9.23 The network in Figure 9.39 of the textbook has a serial line w  between the MUX and DEMUX that is described as:  w = xi if i = 4a + 2b + c and E1 = 1 9:7 0 otherwise The outputs of the DEMUX are speci ed as: yi = w if i = 4a + 2b + c and E2 = 1 0 otherwise Combining both equations we obtain:  9:8 yi = xi if i = 4a + 2b + c and E1 = E2 = 1 0 otherwise  9:9 So, yi is the same as xi or is zero. This circuit is useful to allow the sharing of the single line between Mux and Demux among all pairs of input,output: x0 ; y0 , x1 ; y1  ... and so on. It's used in communication lines to divide the full capacity of the communication line among the many transmitters and receivers. Each pair can communicate without interference of the other pairs. Exercise 9.24 From the network we obtain: 00 0 Y0 = x0y1 S1 + x0 y1S1 + xy1 S3 + xy1S2 + S0 00 0 0 0 00 = x0 y1 y2 y0 0 + x0 y1 y2 y0 + xy1 y2 y0 + xy1 y2 y0 + y2 y0  0 00 0 0 0 = x0 y1 y2 + x0 y1 y0 + x0 y1 y2 y0 + xy1 y2 y0 + xy1 y0 0 0 Y1 = x0y1 S3 + S0  + x0 y1 S2 + S0  + xy1 S0 + xy1 S3 + S2 0 00 0 00 000 0 = x0 y1 y2 y0 + y2 y0  + x0 y1 y2 y0 + y2 y0  + xy1 y2 y0 + xy1 y2 y0 + y2 y0  0 000 0 000 = x0 y1 y2 y0 + x0 y1 y2 y0 + x0 y1 y0 + xy1 y2 y0 + xy1 y2 184 Solutions Manual - Introduction to Digital Design - March 22, 1999 0 0 Y2 = x0y1S0 + S1 + x0 y1 S1 + xy1 S0 + xy1 S1 + S0  0 00 0 0 000 00 0 = x0 y1 y2 y0 + y2 y0  + x0 y1 y2 y0 + xy1 y2 y0 + xy1y2 y0 + y2 y0  00 0 000 0 = x0 y1 y2 + x0 y1 y2 y0 + xy1 y2 y0 + xy1 y2 0 0 00 00 00 z = y2  y0 y1 x = y2 y0 + y2 y0 y1 x = xy2 y1 y0 + y2 y1 y0 From these expressions we following state transition and output table: State PS Input Number y2 y1 y0 x = 0 x = 1 0 000 111,0 110,0 1 001 100,0 000,1 2 010 010,0 101,0 3 011 101,0 100,0 4 100 001,0 000,1 5 101 011,0 001,0 6 110 010,0 011,0 7 111 000,0 010,0 NS Y2 Y1 Y0 ,z To reduce the number of states we use the minimization procedure presented in Section 7.6 of the textbook. The rst partition is: 1 2 x14023567 011222222 122221122 Second partition: 1 2 3 x14026735 011222233 122233211 Third partition: 1 2 3 4 x14072635 011223344 122334411 No more new partitions! Stop. The reduced sequential system has only 4 states. We rename the states as: Sate number State name 1,4 A 0,7 B C 2,6 3,5 D and obtain the following state transition and output table: Solutions Manual - Introduction to Digital Design - March 22, 1999 185 Input x=0 x=1 A A,0 B,1 B B,0 C,0 C C,0 D,0 D D,0 A,0 NS,z A state diagram for the system is shown in Figure 9.23 and corresponds to a modulo-4 counter. 0/0 0/0 PS 1/1 A B 1/0 1/0 1/0 D C 0/0 0/0 Figure 9.23: State digram for Exercise 9.24 A better canonical implementation of this sequential circuit is shown in Figure 9.24 and it uses only two memory elements and some gates. The design steps are not shown. y0 x Y1 y1 z Y0 x Figure 9.24: Redesign of sequential system in Exercise 9.24 Exercise 9.25 From the circuit presented in the gure we can obtain the state diagram in Figure 9.25. The binary decoder connected to the state register generates the signals Si , which is 1 when the sequential system is at state i. The system outputs correspond to the state signals, that means, each output is active in one particular state. For this reason we used the output names as 186 Solutions Manual - Introduction to Digital Design - March 22, 1999 state names to make the state diagram more meaningful. In each present state we identify which input of the binary encoder is 1. This input determines the next state. For example, the origin of arcs going into state S1 check are obtained by considering the input of the Binary Encoder labeled 1, which is S0 for input GO, S2 always, no condition, and S3 always. The state diagram shows the operation of a controller which starts to operate with a GO signal. During operation it monitors two variables: dist and count and issues movement control signals and counter control signals, until dist  10 and count = 3. GO’ dist Initial CLEAR COUNT GO check count = 3  10 6 and turn left dist  10 and count = 3 dist stop move 10 count up Figure 9.25: Exercise 9.25 Exercise 9.26. The codewords of both systems are presented in the following table: n Code A Code B p = 3n mod 16 q = 7n mod 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p2p1p0 0000 0011 0110 1001 1100 1111 0010 0101 1000 1011 1110 0001 0100 0111 1010 1101 q2q1 q0 0000 0111 1110 0101 1100 0011 1010 0001 1000 1111 0110 1101 0100 1011 0010 1001 Solutions Manual - Introduction to Digital Design - March 22, 1999 187 a the design of an A-to-B converter using one 8-input multiplexer and one 2-input XOR gate is shown in Figure 9.26. Observe that: q0 = p0 q1 = p1 q2 = p2  p0 and q3 is easily implemented using an 8-input multiplexer from the following function table: p3 p2p1p0 q3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 p0 p1 p2 q0 q1 q2 0 1 1 0 0 1 2 3 MUX 4 5 6 7210 q3 p3 p2 p1 Figure 9.26: Code converter - Exercise 9.26 a b the code converter designed using one 4-input decoder and one 16-input encoder is shown in Figure 9.27. 188 Solutions Manual - Introduction to Digital Design - March 22, 1999 p0 p1 p2 p3 0 1 2 3 Binary decoder 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary encoder 0 1 2 3 q0 q1 q2 q3 E 1 1 E Figure 9.27: Code converter - Exercise 9.26 b ...
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## This note was uploaded on 10/31/2009 for the course EE EE M16 taught by Professor Eshaghian,m.m. during the Fall '09 term at UCLA.

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