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Unformatted text preview: 99 Chapter 7
Exercise 7.1 Input: Output: Function:
xt 2 fa; b; cg z t 2 fp; qg z t = q if number of a's in x0; t , 1 is even and number of b's is odd. p otherwise
State: st = sa t; sb t sat = number of a's mod 2 sb t = number of b's mod 2
Initial state: sa 0 = 0 sb 0 = 0
Transition function: sa t + 1 = sb t + 1 =
Output function:
sa t0 sa t sb t0 sb t if xt = a otherwise if xt = b otherwise q if st=0,1 z t = p otherwise The state transition and output table is shown below. The state diagram for the system is presented in Figure 7.1 on page 100. Input PS x = a x = b x = c 0,0 1,0 0,1 0,0 p 0,1 1,1 0,0 0,1 q p 1,0 0,0 1,1 1,0 1,1 0,1 1,0 1,1 p NS Output z 100 Solutions Manual  Introduction to Digital Design  February 3, 1999 c b (0,0)/p b c (0,1)/q a a b (1,0)/p b a a (1,1)/p c c Figure 7.1: State Transition Diagram of Exercise 6.1
Exercise 7.2 Input: decimal digit xt 2 f0; 1; 2; 3; 4; 5; 6; 7; 8; 9g. Output: z t 2 f0; 1; 2; 3; 4g. Function: z t = t X i=0 xi mod 5 State: st 2 f0; 1; 2; 3; 4g Initial state: s0 = 0 Function: The statetransition and output functions are described by the expressions: st + 1 = st + xt mod 5 z t = st + xt mod 5
Exercise 7.3 State table: PS S0 S1 S2 S3 S4 xt x=a x=b S0 ; 01 S1; 11 S2 ; 11 S3; 00 S3 ; 11 S3; 11 S3 ; 00 S4; 01 S4 ; 01 S0; 00 NS , z Solutions Manual  Introduction to Digital Design  February 3, 1999 101 Exercise 7.4 The state diagram for this exercise is shown in Figure 7.2 on page 101.
a/0 a/0 c/0 b/1 A c/1 b/1 c/1 E b/1 a/0 c/0 D B b/1 c/1 b/1 C a/0 a/0 Figure 7.2: State Transition Diagram of Exercise 7.4
Exercise 7.5 The state diagram for this exercise is shown in Figure 7.3 on page 101
a b,c a,c c 2/0 c 0/0 b b c 4/0 3/1 b b a 1/1 a a Figure 7.3: State diagram of Exercise 7.5 102
Exercise 7.6 Solutions Manual  Introduction to Digital Design  February 3, 1999 The state table for this exercise is: PS
0 1 2 3 4 5 6 1 0 1 0 1 0 1 NS Output z From where we obtain the following state transition and output functions: st + 1 = st + xt mod 7 The system is a modulo7 counter whose output is 1 whenever the number of 1's in the input modulo 7 is even There are sixteen possible states. To obtain the state diagram, we rst obtain the state table, by an evaluation of the expressions. To simplify the notation, we label the states with an integer 0 j 15 whose binary representation is the bitvector s3 ; s2 ; s1 ; s0 . The state table is
Exercise 7.7 Input x=0 x=1
0 1 2 3 4 5 6 1 2 3 4 5 6 0 zt = st + 1 mod 2 PS x = 0 x = 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 0 2 4 6 8 10 12 14 Input NS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 z Observe that the state transition function is: st + xt mod 2 mod 16 st + 1 = 2st + 8 Solutions Manual  Introduction to Digital Design  February 3, 1999 103 0 0 15 1 14 0 1 1 13 0 1 12 0 1 1 11 0 10 1 0 9 1 0 1 0 0 1 1 0 1 2 0 1 0 1 0 1 0 1 0 1 5 0 6 3 4 7 8 Figure 7.4: State diagram for Exercise 7.7 The corresponding state diagram is shown in Figure 7.4.
Exercise 7.8 The indicated renaming results is in the following state table Input PS x = 0 x = 1 000 000 100 0 001 100 000 0 010 001 101 0 011 101 001 1 100 010 110 0 101 110 010 0 110 011 111 0 111 111 011 1 NS z From the table we obtain the following expressions: s2 t + 1 = s0t xt si t + 1 = si+1t for 0 i 1 104 Solutions Manual  Introduction to Digital Design  February 3, 1999 z t = s1t s0t
The sequential systems described by each table are: a Mealy machine. The output function is a function of the Present State and of the Input. b Moore machine. The output function does not depend on the input. c Moore machine.
Exercise 7.9 Exercise 7.10 The input has four values; we represent it by the bitvector x1 ; x0 with the following code: a = 00; b = 01; c = 10; and d = 11. There are six states; we represent each one by the bit vector y2 ; y1 ; y0 and each state Si correspond to a code shown in the next table arbitrary: State y2 ; y1 ; y0 S0 001 S1 010 S2 000 S3 011 S4 100 S5 101 The output z has ve integer values. We use binary code for these integers, z2 ; z1 ; z0 . The corresponding state table is 000 001 010 011 100 101 PS x = 00 001,011 011,100 010,000 011,000 100,000 000,010 010,001 000,000 000,000 010,001 001,000 001,000 010,000 010,000 101,000 011,000 101,000 011,000 100,000 100,000 010,000 001,001 100,001 101,000 NS Y2 Y1 Y0 ; Outputz x = 01 x = 10 x = 11 To obtain switching expressions, Karnaugh maps can be used. Since there are ve variables, it is convenient to use 4variable maps and include the 5th variable in the cells. 1 y1 0 0 0 y2 2 y2 y0 0 0 y2 y2 y 0
0 0 1 0 x0 Y2 x1 Y1 0 0 0 y2 y2 0 00 y2 y2 0 0 y 0 0 1 1 1 y1 1 1 0 1 x0 1 y1 1 1 1 0 y2 0 0 0 0 y 0 y2 2 y2 y 1 0 x0 x1 Y0 0 0 1 0 x1 Solutions Manual  Introduction to Digital Design  February 3, 1999 105
0 0 y2 y2 0 0 y2 0 1 0 y 0 x0
00 0 y2 0 y1 0 0 00 0 0 0 0 0 0y 0 0 0 y1 0 0 0 0
0000 00 y2 0 0 0 y2 0 0 y0 x0 x0 y1 0 0 0 0
0000 z2 Y2 Y1 Y0 z2 z1 z0
Exercise 7.11 x1
= = = = = = z1 x1 z0 x1 The expressions are:
0 0 00 00 0 x1x0 y1y0 + x1x00 y1y0 + x01y1 y0 y2 + x00 y1 y0 y2 + x1 y1y0y2 0 0 00 0 x01y1 + y1y0 x0 + y1y0 x00 + y0 x01y2 + y1 y0x0 y2 00 00 0 x01x00 y1 y2 + y0 y0 y2 + x01 x0 y1y0y2 + y1 y0 + y0x1 x0 + y1 x1 x0 00 x01 x00 y1 y0 y2 000 0 x01 x00 y2 y1 y0 + x01 x00 y2 y1y0 0 00 0 y1y0 x1x0 y2 + y2 y1y0x01 + y1y0 x01 x0 The time behavior of the modulep counter is given by the arithmetic expressions z t =
where SIN be: t X i=0 s0 + xt mod p s0 = SIN 2 f0; 1; : : : ; p , 1g and xt 2 f0; 1g Exercise 7.12 The number of possible input sequences starting at time t1 = 5 and going up to t2 = 16 would 216,5+1 = 212 possible input sequences As it's possible to have the system in two di erent states at time t1 , S3 or S1 , for the same input sequence it's possible to get two possible sequence pairs. So, the number of sequence pairs needed to describe the system would be: 2 212 = 213 Calling the states by their number e.g. S2 is called 2, three possible sequence pairs are: t xt st z t 5 1 3 c 6 1 3 c 7 0 3 c 8 0 1 a 9 1 2 b 10 1 2 b 11 1 2 b 12 0 2 b 13 1 0 a 14 1 1 a 15 0 3 c 16 1 1 a 106 Solutions Manual  Introduction to Digital Design  February 3, 1999 t xt st z t t xt st z t
Exercise 7.13 5 1 3 c 5 1 1 a 6 1 3 c 6 1 3 c 7 0 3 c 7 0 3 c 8 1 1 a 8 1 1 a 9 1 3 c 9 1 3 c 10 0 3 c 10 1 3 c 11 1 1 a 11 0 3 c 12 1 3 c 12 0 1 a 13 0 3 c 13 1 2 b 14 0 1 a 14 1 2 b 15 1 2 b 15 1 2 b 16 0 2 b 16 1 2 b The state diagram of Figure 7.11a of the textbook results in the following state table: PS Sinit S0 S1 S00 S01 S10 S11
From the table we get S0 ; 0 S1 ; 0 S00 ; 0 S01 ; 0 S10 ; 0 S11 ; 0 S00 ; 0 S01 ; 0 S10 ; 0 S11 ; 0 S00 ; 0 S01 ; 1 S10 ; 0 S11 ; 0 NS; Output 0 Input 1 P1 = Sinit; S0 ; S1; S00 ; S01 ; S11 S10 To obtain P2 , we determine the group of states P1 to which the successors of each state belong.
group 2 Sinit ; S0 ; S1 ; S00 ; S01 ; S11 S10 0 112122 1 1 111111 1 Consequently, group 1 belong. P2 = Sinit ; S0 ; S00S1 ; S01 ; S11 S10 To obtain P3 , we determine the group of states of P2 to which the successors of each state
group 3 Sinit ; S0 ; S00 S1 ; S01 ; S11 S10 0 111 333 1 222 222 2 1 group 1 group 2 Thus, P3 = P2 = P = Sinit ; S0 ; S00 S1 ; S01 ; S11 S10 = Sinit ; A; B Using this partition we construct the state table from the original table: Solutions Manual  Introduction to Digital Design  February 3, 1999 107 0 1 PS Sinit Sinit; 0 A; 0 A B; 0 A; 0 B Sinit; 0 A; 1 NS; Output The corresponding state diagram is equivalent to the one presented in Figure 7.11b of the textbook, thus both diagrams represent the same system.
Exercise 7.14 Input The loose description has eight states as follows: st = A if xt , 1 = a and of a0 s is even st = B if xt , 1 = a and of a0 s is odd st = C if xt , 2; t , 1 = ab and of a0 s is even st = D if xt , 2; t , 1 = ab and of a0 s is odd st = E if xt , 3; t , 1 = abc and of a0 s is even st = F if xt , 3; t , 1 = abc and of a0 s is odd st = G if xt , 3; t , 1 = other and of a0s is even st = H if xt , 3; t , 1 = other and of a0 s is odd The corresponding state table is PS A B C D E F G H
From the table we get Input x=a x=b x=c B; 0 C; 0 G; 0 A; 0 D; 0 H; 0 B; 0 G; 0 E; 0 A; 0 H; 0 F; 0 B; 0 G; 0 G; 0 A; 1 H; 0 H; 0 B; 0 G; 0 G; 0 A; 0 H; 0 H; 0 NS; Output P1 = A; B; C; D; E; G; H F To obtain P2 , we determine the class of P1 to which each successor of the states belong.
1 2 A; B; C; D; E; G; H F a 1111111 1 1111111 1 b c 1112111 1 Consequently, To obtain P3 , we repeat the process P2 = A; B; C; E; G; H DF 108 Solutions Manual  Introduction to Digital Design  February 3, 1999 a b c
Thus, And once more, A; B; C; E; G; H D F 111111 1 1 121111 1 1 111111 3 1 1 2 3 P3 = A; C; E; G; H B DF
1 2 3 A; C; E; G; H B D a 22221 1 1 b 11111 3 1 c 11111 1 4 So Still not ready! Once more hopefully the last P4 = A; C; E; GH B DF 1 2 3 4 5 A; C; E; G B D F H a 2222 1 1 1 1 b 1111 3 5 5 5 1111 5 4 5 5 c So, nally! and the reduced table is P = P5 = P4 = A; C; E; GB DF H Input PS x = a x = b x = c A B; 0 A; 0 A; 0 B A; 0 D; 0 H; 0 D A; 0 H; 0 F; 0 F A; 1 A; 0 A; 0 H A; 0 H; 0 H; 0 NS; Output Exercise 7.15 From the state table we get P1 = a; b; c; ed; hf g To obtain P2 , we determine the class of P1 to which the successors of the states belong.
1 2 34 a; b; c; e d; h f g 0 3232 44 3 4 1 1111 11 1 2 Solutions Manual  Introduction to Digital Design  February 3, 1999 109 Thus, P2 = a; cb; ed; hf g To obtain P3 , we determine the group of states of P2 to which the successors of the state belong.
a; c b; e d; h f g 44 33 55 4 5 22 11 11 2 3 Therefore, P = P3 = P2 = a; cb; ed; hf g and the reduced table is 0 1 1 2 3 4 5 Input PS x = 0 x = 1 a f; 0 b; 0 b d; 0 a; 0 d g; 1 a; 0 f f; 1 b; 1 g g; 0 d; 1 NS; Output
Exercise 7.16 Based on the outputs for each state we get the rst partition P1 as: P1 = A; D; E B; F; GC; H Let's call A,D,E as group 1, B,F,G as group 2 and C,H as group 3. We can construct a table representing the next group for each state transition: group 1 group 2 group 3 02223333 3 13331111 1 From the table we can see that the columns for each group of states are the same, and so, the states in each group are also 2equivalent. P2 = P1 . Renaming the states in group 1 as , the states in group 2 as and in group 3 as , we can represent the reduced sequential system as: ADEBFGC H PS Input x=0 x=1 ;0 ;0 ;1 ;1 ;0 ;1 Based on the outputs for each state we get the rst partition P1 = A; C; G; H B; D; E F To obtain P2 , we determine the class of P1 to which the successors of the states belong. Exercise 7.17 110 Solutions Manual  Introduction to Digital Design  February 3, 1999 a b c d
Partition P2 is ACGHBDE
2 1 2 2 2 1 2 3 2 1 2 3 2 1 2 3 1 3 2 2 1 3 2 2 1 3 2 2 group 1 group 2 group 3 F group 1 a b c d
Partition P3 is A CGHBDE
3 1 3 4 3 1 3 4 3 2 3 4 2 4 3 3 2 4 3 3 2 4 3 3 group 2 group 3 group 4 F group 1 group 2 group 3 a b c d A C
4 1 4 5 G
4 1 4 5 H BDE
2 5 4 4 2 5 4 4 2 5 4 4 group 4 group 5 F STOP. The equivalent states are: fAg, fB,D,Eg, fC,Gg, fFg, fHg Minimal state transition table: PS x = a x = b x = c x = d A B=1 C=0 B=1 B=1 B C=0 F=1 B=1 B=0 C B=1 A=0 B=1 F=1 F C=1 F=1 B=0 H=0 H B=1 C=0 B=1 F=1 NS=output Exercise 7.18 Based on the outputs for each state we get the rst partition P1 = N; O; Q; R; X; Z P; U; V; Y S; T; W
To obtain P2 , we determine the class of P1 to which the successors of the states belong. group 1 group 2 group 3 a333333222211 b122211111122
Partition P2 is NOQRXZPUVYSTW
1 2 Solutions Manual  Introduction to Digital Design  February 3, 1999 111 NXZOQRPUVYSTW a4444443333111 b1113332211333
Partition P3 is group 1 group 2 group 3 group 4 a5 b1
Partition P4 is NXZOQRP
5 1 55 14 554 442 group 1 group 2 group 3 group 4 U
4 2 V 3 1 Y 3 1 STW
11 44 1 3 group 5 a5 b1 N Z
7 1 NXZOQRP
6 1 55 14 664 442 group 1 group 2 group 3 group 4 group 5 group 6 U
4 2 V 3 1 Y 3 1 S
1 4 T 1 4 W Partition P5 is group 1 group 2 group 3 group 4 group 5 group 6 group 7 group 8 a7 b1 X O QRP
8 6 8 6 6 4 U
6 4 V 5 1 Y 5 1 S
1 6 T 1 6 W STOP! Equivalent states: fN,Zg, fOg, fP,Ug, fQ,Rg, fS,Tg, fV,Yg, fWg, fXg Minimal state transition table: PS N O P Q S V W X
Exercise 7.19 input x = a x = a0 S=f N=e S=f V=e V=e Q=f W=f V=e N=e V=e P=f N=f X=e P=e W=f N=e NS=output Input: xt 2 fa; b; c; dg Output: z t 2 f0; 1g State: Since the pattern to be recognized has four symbols, using the vectorstate approach, we represent the state as the vector s = s2 ; s1 ; s0 and the states are st 2 f0; 1; 2; :::; 7g. 112 Solutions Manual  Introduction to Digital Design  February 3, 1999 Function: The corresponding state transition and output functions are: sit + 1 = si,1 t 1 i 2 s0 t + 1 = xt zt = st st st st
= = = =
1 0 if st; xt = abca otherwise For the minimumnumberofstates approach, we de ne a state with the following four values: A if xt , 1 = a B if xt , 2; t , 1 = ab C if xt , 3; t , 1 = abc D if none of the above Initial a A; 0 A; 0 A; 1 A; 0 Input b c B; 0 D; 0 D:0 C; 0 D; 0 D; 0 D; 0 D; 0 NS; z d D; 0 D; 0 D; 0 D; 0 The state description is given by the following table: PS A B C D The output sequence corresponding to the given input sequence is xt a a b c a b c a d a a a b c a st D A A B C A B C A D A A A B C A z t 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1
Exercise 7.20 It is not possible to have a sequential system with m , 1 states recognizing a sequence of length m. As a proof, consider a pattern of length 2, let us say ab. The state diagram for this sequential system is shown in Figure 7.5. We can easily see from the diagram that the states are not equivalent, since their outputs are di erent. Thus, it is not possible to have a reduced state machine with only ONE state to recognize the pattern with length 2. We now consider the generation of a mstate machine to recognize a sequence of length m. Let the pattern to be recognized be p1 p2 : : : pm . The state description of the pattern recognizer is obtained by having m states labeled S0 to Sm,1 as follows: S0 is the initial state. Other states are st = Si whenever the sequence xt,i; t,1 = p1 p2 : : : pi , i 0 that is already i symbols of the pattern have been recognized. The statetransition function is 8 Si+1 if st = Si and xt = pi+1 S if st = Si and pi,j +2 pi,j +3 : : : pi xt = p1 p2 pj ; j 2 st + 1 = Sj if xt = p : S0 1 1 otherwise Solutions Manual  Introduction to Digital Design  February 3, 1999 113 a’/0 a/0 S0 a/0 S1 b/1,a’/0,b’/0 Figure 7.5: Exercise 7.20 and the output function z= 1 0
Exercise 7.21 if st = Sm,1 and xt = pm otherwise The state diagram that describes the system is presented in Figure 7.6 page 113, using the minimum state approach. The vector state approach is not possible to be used since the system is not a nite memory system.
b,c,d/1 a/1 a/1 a/1 b/1 c/1 Even a c,d/1 ab b,d/1 abc b,c,d/1 a/0 b,c,d/0 a/0 a/0 a/0 b/0 c/0 a/1 Odd a c,d/01 ab b,d/01 abc b,c,d/0 Figure 7.6: State Diagram for Exercise 7.21 114
Exercise 7.22 Solutions Manual  Introduction to Digital Design  February 3, 1999 The input set is I = f0; 1; 2; 3; 4; 5; 6; 7; 8; 9g and the output set 0 = f0; 1; 2; 3; 4g. The state is formed of two components: s1 to detect the pattern 358, and s2 to count mod 5 the number of instances. For the pattern recognizer, we need three states as follows: s1 t s1 t s1 t s1 0
8 : = = = = A if xt , 1 = 3 B if xt , 2; t , 1 = 35 C if none of above C
if if The state description of this component is s1t + 1 = A B C xt = 3 s1t = A and xt = 5 otherwise The second component is a modulo 5 counter. Consequently, the state has ve values which we label with the integers 0; 1; 2; 3 and 4 to be able to write the state transition as the arithmetic expression: t s2t + 1 = s2 + 1 mod 5 s2 t s20 = 0
Finally, the output function is z t = s2 t.
Exercise 7.23 if s1 t = B and xt = 8 otherwise Following the hint given in the exercise, the sequential system is decomposed into two. System A recognizes the pattern 0110, and system B recognizes the pattern 1001, as shown in Figure 7.7. The output z t is de ned as a function of the system A states SA t and system B states SB t as follows: SB t zt SAt f0; 1; 2; 3g 0 4 f0; 1; 2; 3g 1 4 4 2 The timing behavior for the given input sequence, considering st = SA t; SB t is: t 0 1 2 3 4 5 6 7 xt 0 0 1 0 1 1 1 0 st 0,0 1,0 2,1 1,2 2,1 3,1 0,1 1,2 z t 0 0 0 0 0 0 0 0 t 8 9 10 11 12 13 14 15 xt 1 1 0 0 1 0 1 0 st 2,1 3,1 4,2 4,3 4,4 4,4 4,4 4,4 z t 0 0 1 1 2 2 2 2 Solutions Manual  Introduction to Digital Design  February 3, 1999 115 System A
1 0 0 1 4 0 3 0 1 1 0 2 1 0 0 1 System B
1 1 0 4 1 3 0 1 2 0 Figure 7.7: State Transition Diagram of Exercise 7.23 Since two di erent patterns are generated, the system consists of two independent pattern generators, let's call these systems A and B . The corresponding state diagram is given in Figure 7.8. The states SA i belongs to system A and states SB i belongs to system B .
/A
Exercise 7.24 S0 A /G S1 A /O S2 A /blank S3 A /U S4 A /C S5 A /L S6 A /N S0 B 1/R SB 1 /U S2 B 0/blank Figure 7.8: State diagram of Exercise 7.24
Exercise 7.25 To make the design simple and tractable, we make the following assumptions: Selection of stamps to buy is the rst step If amount of accumulated coins is at least 15c greater than the face value of the selected stamp, return all coins Then the inputs and outputs are as follows ref. Figure 7.9:
Inputs: Reset : 2 fT; F g 116 Solutions Manual  Introduction to Digital Design  February 3, 1999 CoinType : 2 fN; D; Qg StampType : 2 fS 120c; S 240c; S 350cg ReturnCoinRequest : 2 fT; F g
Outputs: RS 1 RS 2 RS 3 RC RN RD , , , , , , Release stamp 1 20c Release stamp 2 40c Release stamp 3 50c Return Coin Return Nickel Return Dime All outputs take values from the set fT, Fg. The state diagram is shown in Figure 7.10.
Reset Coin Type Stamp Type Return Coin Request Controller RS1 RS2 RS3 RC RN RD Figure 7.9: Inputs & Outputs of Vending Machine Controller Solutions Manual  Introduction to Digital Design  February 3, 1999 117 D / RS1; Q / RS1,RN,RD N/ N/ Select S1,5c S1 Q / RS1, RN Q / RS1, RD D/ S1,10c D/ N/ S1,15c Select Stamp 1 S3/ Wait S1/ N / RS1; D / RS1,RN; Q / RC N / RS2; D / RS2, RN; Q / RC D / RS2; Q / RS2, RN, RD Q/RS2, RD Q / RS2, RN S2 Q/RS2 D/ Select S2 N/ S2,5c N/ S2,10c D/ N/ D/
N/ S2,15c D/
N/ S2,20c D/
N/ S2,25c D/
N/ S2,30c S2,35c Q/
Select Stamp 2 N / RS3; D / RS3, RN; Q / RC D / RS3; Q / RS3, RN, RD Q / RS3, RD Q / RS3, RN Q / RS3 Q/ N/ D/ N/ S3,5c S3,10c Select Stamp 3 Q/ Q/ Select S3 D/
N/ D/
N/ S3,15c Q/ D/
N/ S3,20c Q/ D/
N/ S3,25c D/
N/ S3,30c Q/ D/
N/ S3,35c D/
N/ S3,40c Q/ S3,45c Note: We did not draw the transitions corresponding to inputs RESET and Return Coin Request. Basically, for every state, its next state with the above inputs should be the same  go back to State Wait. In the mean time, RC is true to return all coins deposited so far. Figure 7.10: State Diagram of Exercise 7.25 ...
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This note was uploaded on 10/31/2009 for the course EE EE M16 taught by Professor Eshaghian,m.m. during the Fall '09 term at UCLA.
 Fall '09
 ESHAGHIAN,M.M.

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