{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

chap3

# chap3 - 37 Chapter 3 Exercise 3.1  a logic values...

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 37 Chapter 3 Exercise 3.1 December 10, 1998 a logic values Voltage V Positive Logic Negative Logic 1.0 0 1 4.5 1 0 2.0 unde ned unde ned -1.0 unde ned unde ned b module has the following behavior voltage levels: Positive Logic Negative Logic 0.3 0.3 4.5 4.5 x1 0.2 4.5 0.2 4.5 x0 0.5 4.4 4.4 0.2 z x1 0 0 1 1 x0 0 1 0 1 z 0 1 1 0 z x z x1 1 1 0 0 x0 1 0 1 0 z 1 0 0 1 0 For positive logic, the module is a XOR gate. = 0  1 . For negative logic, the module is a XNOR gate. =  0  1  . x x x Exercise 3.2 We can see from the gure that the switches S1 to S4 form a NAND gate and the switches S5 to S8 implement a NOR gate. The organization of switches is such that we have the NAND and the NOR gate implementations with the outputs connected together. This indicates that the circuit was intended to implement the expressions  + +   =  +  . However, as indicated in the hint, for the case = = 1 and = = 0, there is a path from DD to ground passing through transistors S8, S7, S2, and S1. Consequently, this circuit does not operate correctly. A correct circuit circuit for this function is shown in gure 3.1. ab c d 0 0 a 0 b 0 cd 0 0 a b c d V V DD a c d b z a b c d Figure 3.1: Network the implements the function =  +  z a 0 b 0 cd 0 0 Exercise 3.2 38 Exercise 3.3 Solutions Manual - Introduction to Digital Design - December 10, 1998 abc d 0 The network on Figure 3.21 of the book corresponds to the expression:  +  . This function is implemented using AND and NOR circuits and also complex gates approach as shown in Figure 3.2. V DD a b c d a b c (a) using AND and NOR circuits V DD z d abcd V DD z (b) using complex gate approach Figure 3.2: Function  gure 3.3. Exercise 3.4 abc + d 0 Exercise 3.3 z x0 x1 0 The circuit that implements the function = =  0 + 1  is presented in x 0 x 0 Exercise 3.5 The circuit is similar to the one presented as an example for a transmission gate Figure 3.8 of the textbook. When = 1, the transmission gate in the bottom is ON and the transmission gate at the top is OFF. When = 0, the opposite happens. So, a switching expression for the circuit is: s s z = b:s + a:s 0 Solutions Manual - Introduction to Digital Design - December 10, 1998 V DD 39 x1 x0 z x1 Figure 3.3: Exercise 3.4 - Circuit that implements =  0 + 1  z x 0 x 0 a the output load of gate 1 is 4, since this output is connected to 4 inputs of load 1. b gate 6 has the output connected to two inputs gates 7 and 8 with a total load of 4. The remaining fanout of gate 6 is 4 loads its original Fanout factor is 8. Based on the gure, and knowing that the propagation delay is measured based on 50 of the voltage level transition input to output, the propagation delay time is: Exercise 3.7 Exercise 3.6 pHLNOR tpLH NOR t = 45 = 40 : L : ns : ns Delay of the gate is pHL = 0 43 + 0 15 ns and pLH = 0 35 + 0 25 ns. The input and output waveforms for this gate are presented in Figure 3.4. Exercise 3.9 a For a load factor of = 70 the propagation delays are: Exercise 3.8 t : t : : L L pHL tpLH t : : L ns = 0 43 + 0 15  70 = 10 93 = 0 35 + 0 25  70 = 17 85 : : : : : : ns ns b Using a bu er with load factor of 2 and propagation time given by pHL bu er = pLH bu er = 0 6 + 0 02  , the network consisting of a gate followed by the bu er has a delay: t t t pHLgate&bu tpLH gate&bu er = 0 43 + 0 15  2 + 0 6 + 0 02  70 = 2 73 er = 0 35 + 0 25  2 + 0 6 + 0 02  70 = 2 85 : : : : : : : : : : ns ns c using two bu ers we get: t pHLgate&2-bu tpLH gate&2-bu ers = 0 43 + 0 15  4 + 0 6 + 0 02  35 = 2 33 ers = 0 35 + 0 25  4 + 0 6 + 0 02  35 = 2 65 : : : : : : : : : : ns ns 40 Solutions Manual - Introduction to Digital Design - December 10, 1998 GATE TIMING Input 0.58 0.60 output L=1 0.73 0.85 output L=2 Figure 3.4: Timing diagram, Exercise 3.8 d Optimum number of bu ers can be obtained by the generalization of the delay equation, considering as the number of bu ers: pHL gate&n-bu ers = 0 43 + 0 15  2 + 0 6 + 0 02  d70 e = 1 03 + 0 3 + 0 02  d70 e pLH gate&n-bu ers = 0 35 + 0 25  2 + 0 6 + 0 02  d70 e = 0 95 + 0 5 + 0 02  d70 e The function has a minimum. We can see that for = 3, the delays increase to pHL = 2 41 and pLH = 2 93, when compared to delays for = 2. So, the best number of bu ers is 2, and the load should be distributed in only 2 sets. n t : : n n : : : =n : : :n : : =n =n t : : : =n :n n t : t : n ticks. Exercise 3.10 From the gure we get the time pLH = 3 t ns 12 ticks and pHL = 1 25 t : ns 5 Exercise 3.11 and Noise margins are de ned as:  , Hmin  Hmin  V OU T V V IN  Based on the values Lmax OU T  , VLmax I N  e we obtain the noise margins: and H OU T   f ; a  VH I N   b; g  VL OU T   h; c  VL I N   d V  V Hmin OU T  , VHmin I N  = e , a Lmax OU T  , VLmax I N  = h , d V ...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online