lab5_sp09

lab5_sp09 - ECE337 LAB 5 Spring 2009 Lab 5 - Design of a...

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ECE337 LAB 5 Spring 2009 1 Lab 5 - Design of a Receiver Block for a Universal Asynchronous Receiver/Transmit (UART) In this lab, you will: Design and Test via a Test Bench the timer unit for the Receiver Block of the UART. Design and Test via a Test Bench the Receiver Control Unit (RCU) for the Receiver Block of the UART. Combine the RCU block and other given blocks in order to create the Receiver Block (rcv_block) of the UART. Generate a Test Bench from a given template to test and compare the functionality of the rcv_block created with the GOLD_rcv_block. Synthesize the rcv_block using Synopsys. Test the Synthesized/MAPPED version of the rcv_block Submit electronically your completed UART receiver block to be graded 0. Regarding this lab For this lab, you will be working with a collaborator with whom you are to meet and collaborate on the design and testing of your solution for lab 5. The collaboration ground rules are posted in the Lab Exercises section of Blackboard in the Team Reports document. 1. Copying Setup Files In a UNIX terminal window, issue the following command: setup5 This command is actually an alias to a batch/script file in the ece337/Class0.5u directory that will copy the files that are necessary for the completion of this lab. If you have trouble with this step, please ask for assistance from your TA . 2. General Comments Regarding Lab 5 and the Remaining Labs In Lab 5 you will be working on the design of a Universal Asynchronous Receiver Transmitter, known as a UART. From the first day of class, you have been gathering the knowledge and expertise with the tools to allow you to complete this design. At this point in the course, you should know how to operate all the tools that were introduced to you in Labs 1 through 4. From this point onwards in the class, the TAs will not provide any help on problems that the student should be able to correct on their own. If you require a TA to fix an error that is deemed something the student should know how to do, a point deduction will be enforced. In addition, up to this point, you have been introduced to all the VHDL syntax and constructs that are needed to implement the Receiver Block of the UART. That is to say that with the knowledge of VHDL that you have you should be able to complete this design.
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ECE337 LAB 5 Spring 2009 2 This lab is structured to mimic what you would encounter should you choose to pursue a career as an ASIC/VLSI designer upon graduation. Essentially, you, the designer, are being provided with a set of specifications for 9 blocks, the Receiver Block and the 8 building blocks of the Receiver Block. In industry, you will most likely working together with other people in designing your ASIC. Therefore some blocks in your design will be written by other people and you will be required to
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lab5_sp09 - ECE337 LAB 5 Spring 2009 Lab 5 - Design of a...

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