xapp709 - Application Note: Virtex-4 Family R DDR SDRAM...

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XAPP709 (v2.0) October 27, 2006 www.xilinx.com 1 © 2004–2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Summary This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10C device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines. DDR SDRAM devices are low-cost, high-density storage resources that are widely available from many memory vendors. This reference design has been developed using both SDRAM components and DIMMs. DDR SDRAM Description The DDR SDRAM specification details are available from JEDEC organization, part of the Electronic Industries Alliance (EIA), at http://www.jedec.org / . The DDR SDRAM specifications are published in the JEDEC document, under the reference JESD79E. DDR SDRAM devices are the silicon memory resource most frequently used in systems today, with applications ranging from consumer products to video systems. DDR SDRAM device frequencies range up to 200 MHz or DDR400. DRAM devices are available in component or module configurations. DDR Controller Commands Table 1 presents the commands issued by the controller. These commands are passed to the memory using the following control signals: Row Address Select (RAS ) Column Address Select (CAS ) Write Enable (WE ) Clock Enable (CKE) (always held High after device configuration) Chip Select (CS ) (always held Low during device operation) Application Note: Virtex-4 Family XAPP709 (v2.0) October 27, 2006 DDR SDRAM Controller Using Virtex-4 FPGA Devices Author: Rich Chiu R Table 1: DDR SDRAM Commands Signal No. Function RAS CAS WE 1 Load Mode Register L L L 2 Auto Refresh L L H 3 Precharge (1) LHL 4 Select Bank Activate Row L H H 5 Write Command H L L 6 Read Command H L H
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2 www.xilinx.com XAPP709 (v2.0) October 27, 2006 DDR SDRAM Description R Command Functions Mode Register The Mode register is used to define the specific mode of DDR SDRAM operation, including the selection of burst length, burst type, CAS latency, and operating mode. Figure 1 shows the Mode register features that this controller uses.
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xapp709 - Application Note: Virtex-4 Family R DDR SDRAM...

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