Lec04 - Review Instruction Set Overview Classifying...

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1 Review Instruction Set Overview Classifying Instruction Set Architectures (ISAs)
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2 Memory Addressing ° Since 1980 almost every machine uses addresses to level of 8-bits (byte) ° 2 questions for design of ISA: Read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address, how do byte addresses map onto words? Can a word be placed on any byte boundary? CPU Address Bus Word 0 (bytes 0 to 3) Word 1 (bytes 0 to 3)
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3 Memory is byte addressed and provides access for bytes (8 bits), half words (16 bits), words (32 bits), and double words(64 bits). Addresses Specify Byte Locations Address of the first byte in word Successive word addresses differ by 4 (32-bit) 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 32-bit Words Bytes Addr. 0012 0013 0014 0015 64-bit Words Addr = ?? Addr = ?? Addr = ?? Addr = ?? Addr = ?? Addr = ?? 0000 0004 0008 0012 0000 0008 Memory Addressing
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4 Addressing Objects: Endianess and Alignment Big Endian : address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha (Windows NT) Alignment: require that objects fall on address that is multiple of their size. 0 1 2 3 Aligned Not Aligned 0x100 0x101 0x102 0x103 01 23 45 67 0x100 0x101 0x102 0x103 67 45 23 01 Big Endian Little Endian 01 23 45 67 67 45 23 01
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5 Reading Byte-Reversed Listings Disassembly Text representation of binary machine code Generated by program that reads the machine code Example Fragment Address Instruction Code Assembly Rendition 8048365: 5b pop %ebx 8048366: 81 c3 ab 12 00 00 add $0x12ab,%ebx 804836c: 83 bb 28 00 00 00 00 cmpl $0x0,0x28(%ebx) Deciphering Numbers Value: 0x12ab Pad to 4 bytes: 0x000012ab Split into bytes: 00 00 12 ab Reverse: ab 12 00 00
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6 Types of Addressing Modes (VAX) Addressing Mode Example Action 1. Register direct Add R4, R3 R4 <- R4 + R3 2. Immediate Add R4, #3 R4 <- R4 + 3 3. Displacement Add R4, 100(R1) R4 <- R4 + M[100 + R1] 4. Register indirect Add R4, (R1) R4 <- R4 + M[R1] 5. Indexed Add R4, (R1 + R2) R4 <- R4 + M[R1 + R2] 6. Direct Add R4, (1000) R4 <- R4 + M[1000] 7. Memory Indirect Add R4, @(R3) R4 <- R4 + M[M[R3]] 8. Autoincrement Add R4, (R2)+ R4 <- R4 + M[R2] R2 <- R2 + d 9. Autodecrement Add R4, (R2)-
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Lec04 - Review Instruction Set Overview Classifying...

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