Lec08 - The Problem with Single-Cycle Processor...

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1 The Problem with Single-Cycle Processor Implementation: Performance Performance is limited by the slowest instruction Example: suppose we have the following delays Memory read/write 200ps ALU and adders 100ps Register File read/write 50ps What is the critical path for each instruction?
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2 What is the critical path for lw? lw: 200 + 50 + 100 + 200 + 50 600ps P C address Inst. R1 (rt) R2 (rs) -100 lw ReadRegister#1 ReadRegister#2 WriteRegister Data Port#1 Port#2 ALU REGISTERS ROM Instruction Memory Data Memory RAM DataIn Address DataOut 16 (Imm) SIGN-EXTEND 16 32 Memory read/write 200ps ALU and adders 100ps Register File read/write 50ps
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