Lec10 - Full Multicycle Datapath IRWrite I R PCWr* IorD...

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1 Full Multicycle Datapath 5 5 RD1 RD2 RN1 RN2 WN WD RegWrite Registers Operation ALU 3 E X T N D 16 32 Zero RD WD MemRead Memory ADDR MemWrite 5 Instruction I 32 ALUSrcB <<2 PC 4 RegDst 5 I R M D R M U X 0 1 2 3 M U X 1 0 M U X 0 1 A B ALU OUT 0 1 2 M U X <<2 CONCAT 28 32 M U X 0 1 ALUSrcA jmpaddr I[25:0] rd MUX 01 rt rs immediate PCSource MemtoReg IorD PCWr* IRWrite
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2 Our new datapath We eliminate both extra adders in a multicycle datapath, and instead use just one ALU, with multiplexers to select the proper inputs. A 2-to-1 mux ALUSrcA sets the first ALU input to be the PC or a register. A 4-to-1 mux ALUSrcB selects the second ALU input from among: the register file (for arithmetic operations), a constant 4 (to increment the PC), a sign-extended constant (for effective addresses), and a sign-extended and shifted constant (for branch targets). This permits a single ALU to perform all of the necessary functions. Arithmetic operations on two register operands. Incrementing the PC. Computing effective addresses for lw and sw. Adding a sign-extended, shifted offset to (PC + 4) for branches.
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3 Full Multicycle Implementation ALU Control Control Unit 66 op I[31:26] funct I[5:0] ALUOp 2 5 5 RD1 RD2 RN1 RN2 WN WD RegWrite Registers Operation ALU 3 E X T N D 16 32 Zero RD WD MemRead Memory ADDR MemWrite 5 Instruction I 32 ALUSrcB <<2 PC 4 RegDst 5 I R M D R M U X 0 1 2 3 M U X 1 0 M U X 0 1 A B ALU OUT 0 1 2 M U X <<2 CONCAT 28 32 M U X 0 1 ALUSrcA jmpaddr I[25:0] rd MUX 01 rt rs immediate PCSource MemtoReg IorD PCWriteCond PCWrite Zero IRWrite
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4 Historical Perspective In the ‘60s and ‘70s microprogramming was very important for implementing machines This led to more sophisticated ISAs and the VAX In the ‘80s RISC processors based on pipelining became popular Pipelining the microinstructions is also possible! Implementations of IA-32 architecture processors since 486 use: “hardwired control” for simpler instructions (few cycles, FSM control implemented using PLA or random logic) “microcoded control” for more complex instructions
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This note was uploaded on 11/03/2009 for the course CS 20929 taught by Professor Taoxie during the Spring '09 term at San Diego State.

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Lec10 - Full Multicycle Datapath IRWrite I R PCWr* IorD...

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