Lec11 - 1 Pipeline: Hazards Fall, 2009 These slides are...

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Unformatted text preview: 1 Pipeline: Hazards Fall, 2009 These slides are adapted from notes by Dr. David Patterson (UCB) 2 Single-Cycle vs. Pipelined Execution on-Pipelined 200 400 600 800 1000 1200 1400 1600 1800 lw $1, 100($0) Instruction Fetch REG RD ALU REG WR MEM lw $2, 200($0) Instruction Fetch REG RD ALU REG WR MEM lw $3, 300($0) Instruction Fetch Time Instruction Order 800ps 800ps 800ps ipelined 200 400 600 800 1000 1200 1400 1600 lw $1, 100($0) Instruction Fetch REG RD ALU REG WR MEM lw $2, 200($0) lw $3, 300($0) Time nstruction rder 200ps Instruction Fetch REG RD ALU REG WR MEM Instruction Fetch REG RD ALU REG WR MEM 200ps 200ps 200ps 200ps 200ps 200ps 3 Speedup Consider the unpipelined processor introduced previously. Assume that it has a 1 ns clock cycle and it uses 4 cycles for ALU operations and branches , and 5 cycles for memory operations , assume that the relative frequencies of these operations are 40%, 20%, and 40%, respectively. Suppose that due to clock skew and setup, pipelining the processor adds 0.2ns of overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline? Average instruction execution time = 1 ns * ((40% + 20%)*4 + 40%*5) = 4.4ns Speedup from pipeline = Average instruction time unpiplined/Average instruction time pipelined = 4.4ns/1.2ns = 3.7 4 Comments about Pipelining The good news Multiple instructions are being processed at same time This works because stages are isolated by registers Best case speedup of N The bad news Instructions interfere with each other - hazards Example: different instructions may need the same piece of hardware (e.g., memory) in same clock cycle Example: instruction may require a result produced by an earlier instruction that is not yet complete 5 Pipeline Hazards Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle Structural hazards : two different instructions use same h/w in same cycle Data hazards : Instruction depends on result of prior instruction still in the pipeline Control hazards : Pipelining of branches & other instructions that change the PC 6 Structural Hazards Attempt to use same resource twice at same time Example: Single Memory for instructions, data Accessed by IF stage Accessed at same time by MEM stage Solutions ?...
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This note was uploaded on 11/03/2009 for the course CS 20929 taught by Professor Taoxie during the Spring '09 term at San Diego State.

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Lec11 - 1 Pipeline: Hazards Fall, 2009 These slides are...

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