Lec17 - Instruction-level parallelism: Introduction Dr. Tao...

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1 Instruction-level parallelism: Introduction Dr. Tao Xie Fall, 2009 These slides are adapted from notes by Dr. David Patterson (UCB)
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2 Ideas To Reduce Stalls Technique Reduces Dynamic scheduling Data hazard stalls Dynamic branch prediction Control stalls Issuing multiple instructions per cycle Ideal CPI Speculation Data and control stalls Dynamic memory disambiguation Data hazard stalls involving memory Loop unrolling Control hazard stalls Basic compiler pipeline scheduling Data hazard stalls Compiler dependence analysis Ideal CPI and data hazard stalls Software pipelining and trace scheduling Ideal CPI and data hazard stalls Compiler speculation Ideal CPI, data and control stalls Pipeline CPI = Ideal pipeline CPI + Structure stalls + Data hazard stalls + Control stalls
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3 Forms of Parallelism Process-level Thread-level Loop-level Instruction-level Coarse grain Fine Grain H u m a n i t e r v o ?
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4 Instruction Level Parallelism (ILP) Principle : There are many instructions in code that don’t depend on each other . That means it’s possible to execute those instructions in parallel. Instruction-Level Parallelism ( ILP ): overlap the execution of instructions to improve performance This is easier said than done. Issues include: Building compilers to analyze the code, Building hardware to be even smarter than that code. This section looks at some of the problems to be solved.
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5 Exploiting Parallelism in Pipeline Two methods of exploiting the parallelism ? Today’s high-end microprocessor issues 3 to 8 instructions every clock cycle. Increase pipeline depth Multiple issue Replicate internal components launch multiple instructions in every pipeline stage
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6 Pipeline supports multiple outstanding FP operations M1 M2 M3 M4 M5 M6 M7 Mem WB ID IF A1 A2 A3 A4 Mem WB ID IF EX Mem WB ID IF EX Mem WB ID IF MULTD ADDD LD SD
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7 Microarchitecture of Intel Pentium 4
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8 The Big Picture Parallelism Increase pipeline depth Multiple issue Dynamic multiple issue Static multiple issue Many decisions are made by compiler before execution Many decisions are made by hardware during execution
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9 ILP Challenges How many instructions can we execute in parallel? Definition of Basic instruction block : What is between two branch instructions: Example: Body of a loop. Typical MIPS programs have 15-25 % branch instruction : One every 4-7 instructions is a branch. How many of those are likely to be data dependent on each other?
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Lec17 - Instruction-level parallelism: Introduction Dr. Tao...

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