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Unformatted text preview: ECE 25 Logic and Computer Design Edge-Triggered Flip-Flops 6 D C Q Q’ C S R Q Q’ Out Y Negative Edge-Triggered D C Q Q’ C S R Q Q’ Out Y Positive Edge-Triggered Out Y D Clk Time Out Y D Clk Clk Clk ©Clark Guest 2009 ECE 25 Logic and Computer Design Standard Diagrams 7 D C S R S R D C C S R C S R D C D C D C D C Simple Master-Slave Pulse-Triggered Edge-Triggered ©Clark Guest 2009 ECE 25 Logic and Computer Design Flip-Flops with Direct Inputs 8 Q Q’ R (Reset) S (Set) C Preset’ Clear’...
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- Fall '09
- bill lin
- Logic gate, ©Clark Guest, Qn Q’n Previous