Ch05d-Sequential

Ch05d-Sequential - Clark Guest 2009 ECE 25 Logic and...

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©Clark Guest 2009 ECE 25 Logic and Computer Design A Sequence Recognizer 27 One input: X One output: Z Recognizes sequence of inputs on X: 1101 Z = 1 if previous X values have been 110, and current X value is 1 A B C D 1/0 1/0 1/0 0/0 0/0 0/0 0/0 1/1 ©Clark Guest 2009 ECE 25 Logic and Computer Design Verilog for Sequence Recognizer 28 module seq_rec_v(CLK, RESET, X, Z); input CLK, RESET, X; output Z; reg [1:0] state, next_state; parameter A=2‘b00, B=2‘b01, C=2‘b10, D=2‘b11; reg Z; always @ ( posedge CLK or posedge RESET) begin if (RESET == 1) state <= A; else state <= next_state; end always @ (X or state) begin case (state) A: if (X == 1) next_state <= B; else next_state <= A; B: if (X) next_state<=C; else next_state<=A; C: if (X) next_state<=C; else next_state<=D; D: if (X) next_state<=B; else next_state<=A; endcase end always @ (X or state) begin case (state) A: Z <= 0; B: Z <= 0; C: Z <= 0; D: Z <= X ? 1 : 0; endcase end endmodule ©Clark Guest 2009
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This note was uploaded on 11/03/2009 for the course ECE ECE25 taught by Professor Bill lin during the Fall '09 term at UCSD.

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Ch05d-Sequential - Clark Guest 2009 ECE 25 Logic and...

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