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Unformatted text preview: Gate Propagation Delay 6 V in V out V in V out t PHL t PLH t pd = max(t PHL , t PLH ) 0.8 SL 1.0 SL 1.0 SL t pd = 0.07 + 0.021 x SL ns = 0.07 + 0.021x(0.8+1.0+1.0) = 0.129 ns Wiring can also contribute to delay ©Clark Guest 2009 ECE 25 Logic and Computer Design Flip-Flop Timing 7 t wH ! t wH,min t wL ! t wL,min t s t h t p,min t p,max Clock S, R Q Pulse-triggered t wH ! t wH,min t wL ! t wL,min t s t h t p,min t p,max Clock D Q Edge-triggered ©Clark Guest 2009 ECE 25 Logic and Computer Design Fastest Clock Speed 8 t comb t pd,FF t s Inputs Outputs Combination Logic Flip-Flops Clock t s t pd,FF t comb t slack t s t pd,FF t comb t slack t p Edge-triggered Pulse-triggered t slack " 0, t p " t pd,FF + t comb + t s Clock frequency = 1/t p...
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This note was uploaded on 11/03/2009 for the course ECE ECE25 taught by Professor Bill lin during the Fall '09 term at UCSD.
- Fall '09
- bill lin