Ch07a-Registers

Ch07a-Registers - Clark Guest 2009 ECE 25 Logic and...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Registers and Register Transfers ECE 25 Chapter 7 ©Clark Guest 2009 ECE 25 Logic and Computer Design Topics Multi-bit, parallel-load register Shift registers Counters 2 ©Clark Guest 2009 ECE 25 Logic and Computer Design Multi-bit Register with Parallel Load 3 D C CLR D C CLR D C CLR D C CLR D 0 D 1 D 2 D 3 Load Clear’ Q 0 Q 1 Q 2 Q 3 ©Clark Guest 2009 ECE 25 Logic and Computer Design Multi-bit Register with Enable: Wrong Way 4 D C CLR D C CLR D C CLR D C CLR D 0 D 1 D 2 D 3 Load (or Clock) Clear’ Q 0 Q 1 Q 2 Q 3 Enable Delays in clock lines are bad!
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
©Clark Guest 2009 ECE 25 Logic and Computer Design Multi-bit Register with Enable: Right Way 5 D C CLR EN D 0 D 1 D 2 D 3 Load Clear’ Q 0 Q 1 Q 2 Q 3 D C CLR EN D C CLR EN D C CLR EN Enable D C CLR EN = D C CLR Enable D ©Clark Guest 2009 ECE 25 Logic and Computer Design Shift Register 6 D C CLR D C CLR D C CLR D C CLR Serial Input (SI) Shift Clear’ Serial Output (SO) ©Clark Guest 2009 ECE 25 Logic and Computer Design Bidirectional Shift Register with Parallel Load
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/03/2009 for the course ECE ECE25 taught by Professor Bill lin during the Fall '09 term at UCSD.

Page1 / 4

Ch07a-Registers - Clark Guest 2009 ECE 25 Logic and...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online