Ch08b-Memory

Ch08b-Memory - Clark Guest 2009 ECE 25 Logic and Computer...

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©Clark Guest 2009 ECE 25 Logic and Computer Design DRAM Bit Slice 13 DRAM Cell DRAM Cell DRAM Cell . . . . . . Data In Read/ Write’ Bit Select Data Out B C Word Select Sense Amp B C Select DRAM Cell ©Clark Guest 2009 ECE 25 Logic and Computer Design DRAM Chip 14 SRAM Column SRAM Column SRAM Column Decode Input/Output Logic WS WS WS WS Column Decoder Refresh Controller Refresh Counter Row Addr Register Row Timing Logic Column Timing Logic Column Addr Register . . . . . . . . . Row Addr RAS’ CAS’ Column Addr R/W’ OE’ Data In/ Data Out ©Clark Guest 2009 ECE 25 Logic and Computer Design DRAM Write Timing 15 Clock Addr RAS’ CAS’ OE’ R/W’ Data In T1 T2 T3 T4 T1 Row Addr Column Addr Data Valid ©Clark Guest 2009 ECE 25 Logic and Computer Design DRAM Read Timing 16 Clock Addr RAS’ CAS’ OE’ R/W’ Data Out T1 T2 T3 T4 T1 Row Addr Column Addr Data Valid Hi-Z
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©Clark Guest 2009 ECE 25 Logic and Computer Design DRAM Refresh 17 Charge leaks out of DRAM storage capacitors Every time a read operation takes place
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Ch08b-Memory - Clark Guest 2009 ECE 25 Logic and Computer...

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