cs3330-chap2-isa-3

cs3330-chap2-isa-3 - CS/ECE 3330 Computer Architecture...

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1 CS/ECE 3330 Computer Architecture Chapter 2 ISA Wrap-up ISA An interface: the “deal” between hardware and software Instruction Set Architecture Languages get compiled down to the ISA Hardware must implement the ISA Can be extended, but nothing can be removed! Examples of ISAs CS/ECE 3330 – Fall 2009 x86, AMD64, PA-RISC, ARM, …, MIPS! 1
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2 Translation and Startup Many compilers produce object modules directly CS/ECE 3330 – Fall 2009 2 Registers vs. Memory Registers are faster to access than memory Operating on data in memory requires loads and stores – More instructions to be executed Compiler must use registers for variables as much as possible – Only spill to memory for less frequently used variables –Register optimization is important! CS/ECE 3330 – Fall 2009 3
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3 Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Assembly: symbolic form of machine code Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … CS/ECE 3330 – Fall 2009 4 Pseudoinstructions ± Most assembly instructions represent machine instructions one-to-one ± Pseudoinstructions: figments of the assembler’s imagination (think “macro”) move $t0, $t1 add $t0, $zero, $t1 blt $t0, $t1, L slt $at, $t0, $t1 bne $at, $zero, L ± $at (register 1): assembler temporary CS/ECE 3330 – Fall 2009 5
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4 From C to MIPS Instruction in C: a = b + c; /* a gets b + c */ MIPS arithmetic operations: three operands Two sources and one destination add a, b, c # a gets b + c All arithmetic operations have this form CS/ECE 3330 – Fall 2009 6 From MIPS to Binary: R-format Example op rs rt rd shamt funct 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add 0 17 18 8 0 32 CS/ECE 3330 – Fall 2009 000000 10001 10010 01000 00000 100000 00000010001100100100000000100000 2 = 02324020 16 7
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5 MIPS I-format Instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits Immediate arithmetic and load/store instructions rt: destination or source register number Constant: –2 15 to +2 15 – 1 addi $t0, $s1, 15 CS/ECE 3330 – Fall 2009
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This note was uploaded on 11/04/2009 for the course CS 333 taught by Professor Stankovic during the Fall '08 term at UVA.

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cs3330-chap2-isa-3 - CS/ECE 3330 Computer Architecture...

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