cs3330-chap4-datapath

cs3330-chap4-datapath - CS/ECE 3330 Computer Architecture...

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1 CS/ECE 3330 Computer Architecture Chapter 4 The Processor ± CPU performance factors ² Instruction count – Determined by ISA and compiler CPI and Cycle time Introduction ² – Determined by CPU hardware ± We will examine two MIPS implementations ² A simplified version ² A more realistic pipelined version ± Simple subset, shows most aspects CS/ECE 3330 – Fall 2009 ² Memory reference: lw , sw ² Arithmetic/logical: add , sub , and , or , slt ² Control transfer: beq , j 1
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2 ± PC instruction memory, fetch instruction ± Register numbers register file, read registers Instruction Execution ± Depending on instruction class ² Use ALU to calculate – Arithmetic result – Memory address for load/store – Branch target address ² Access data memory for load/store CS/ECE 3330 – Fall 2009 ² PC target address or PC + 4 2 CPU Overview CS/ECE 3330 – Fall 2009 3
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3 Multiplexers ± Can’t just join wires together ² Use multiplexers CS/ECE 3330 – Fall 2009 4 Control CS/ECE 3330 – Fall 2009 5
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4 ± Information encoded in binary ² Low voltage = 0, High voltage = 1 ² One wire per bit Logic Design Basics ² Multi-bit data encoded on multi-wire buses ± Combinational element ² Operate on data ² Output is a function of input ± State (sequential) elements CS/ECE 3330 – Fall 2009 ² Store information 6 AND-gate Y = A & B Combinational Elements A Adder Y = A + B A B Y Multiplexer Y = S ? I1 : I0 B Y + Arithmetic/Logic Unit Y = F(A, B) CS/ECE 3330 – Fall 2009 7 I0 I1 Y M u x S A B Y ALU F
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5 ± Register: stores data in a circuit ² Uses a clock signal to determine when to update the stored value Sequential Elements ²
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This note was uploaded on 11/04/2009 for the course CS 333 taught by Professor Stankovic during the Fall '08 term at UVA.

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cs3330-chap4-datapath - CS/ECE 3330 Computer Architecture...

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