cs3330-chap4-pipeline-1

cs3330-chap4-pipeline-1 - 1 Pipelined laundry: overlapping...

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Unformatted text preview: 1 Pipelined laundry: overlapping execution Parallelism improves performance Pipelining Analogy 4.5 An Overview o f Pipelining Four loads CS/ECE 3330 Fall 2009 32 Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup = 2n/0.5n + 1.5 4 = number of stages Five stages, one step per stage IF: Instruction fetch from memory ID: Instruction decode & register read MIPS Pipeline EX: Execute operation or calculate address MEM: Access memory operand WB: Write result back to register IF ID EX MEM WB Instr 1 CS/ECE 3330 Fall 2009 33 IF ID EX MEM WB IF ID EX MEM WB Instr 2 Instr 3 Time 2 Assume time for stages is 100ps for register read or write 200ps for other stages Pipeline Performance Compare pipelined datapath with single-cycle datapath Instr Instr fetch Register read ALU op Memory access Register write Total time CS/ECE 3330 Fall 2009 34 lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps) CS/ECE 3330 Fall 2009 35 3 If all stages are balanced i.e., all take the same time Time between instructions pipelined Pipeline Speedup = Time between instructions nonpipelined...
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cs3330-chap4-pipeline-1 - 1 Pipelined laundry: overlapping...

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