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cs3330-chap5-memory-2

cs3330-chap5-memory-2 - Example Intrinsity FastMATH...

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1 Embedded MIPS processor 12-stage pipeline Instruction and data access on each cycle Example: Intrinsity FastMATH Split cache: separate I-cache and D-cache Each 16KB: 256 blocks 16 words/block D-cache: write-through or write-back SPEC2000 miss rates I-cache: 0.4% D h 11 4% CS/ECE 3330 – Fall 2009 D-cache: 11.4% Weighted average: 3.2% 21 Example: Intrinsity FastMATH CS/ECE 3330 – Fall 2009 22
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2 What Happens When We Miss in the Cache? CS/ECE 3330 – Fall 2009 23 Use DRAMs for main memory Fixed width (e.g., 1 word) Connected by fixed-width clocked bus B l k i t i ll l th CPU l k Main Memory Supporting Caches – Bus clock is typically slower than CPU clock Example cache block read 1 bus cycle for address transfer 15 bus cycles per DRAM access 1 bus cycle per data transfer For 4-word block 1-word-wide DRAM CS/ECE 3330 – Fall 2009 For 4-word block, 1-word-wide DRAM Miss penalty = 1 + 4 15 + 4 1 = 65 bus cycles Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle 24
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3 Increasing Memory Bandwidth 4-word wide memory Mi lt 1 15 1 17 b l CS/ECE 3330 – Fall 2009 25 Miss penalty = 1 + 15 + 1 = 17 bus cycles Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle 4-bank interleaved memory Miss penalty = 1 + 15 + 4 × 1 = 20 bus cycles Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle Bits in a DRAM are organized as a rectangular array DRAM accesses an entire row B t d l i d f Advanced DRAM Organization Burst mode: supply successive words from a row with reduced latency Double data rate (DDR) DRAM Transfer on rising and falling clock edges Quad data rate (QDR) DRAM Separate DDR inputs and outputs CS/ECE 3330 – Fall 2009 26
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