cs3330-chap5-memory-2

cs3330-chap5-memory-2 - Example: Intrinsity FastMATH...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ± Embedded MIPS processor ² 12-stage pipeline ² Instruction and data access on each cycle Example: Intrinsity FastMATH ± Split cache: separate I-cache and D-cache ² Each 16KB: 256 blocks 16 words/block ² D-cache: write-through or write-back ± SPEC2000 miss rates ² I-cache: 0.4% CS/ECE 3330 – Fall 2009 ² D-cache: 11.4% ² Weighted average: 3.2% 21 Example: Intrinsity FastMATH CS/ECE 3330 – Fall 2009 22
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 What Happens When We Miss in the Cache? CS/ECE 3330 – Fall 2009 23 ± Use DRAMs for main memory ² Fixed width (e.g., 1 word) ² Connected by fixed-width clocked bus Main Memory Supporting Caches – Bus clock is typically slower than CPU clock ± Example cache block read ² 1 bus cycle for address transfer ² 15 bus cycles per DRAM access ² 1 bus cycle per data transfer For 4-word block 1-word-wide DRAM CS/ECE 3330 – Fall 2009 ± For 4-word block, 1-word-wide DRAM ² Miss penalty = 1 + 4 15 + 4 1 = 65 bus cycles ² Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle 24
Background image of page 2
3 Increasing Memory Bandwidth ± 4-word wide memory CS/ECE 3330 – Fall 2009 25 ± Miss penalty = 1 + 15 + 1 = 17 bus cycles ± Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle ± 4-bank interleaved memory ± Miss penalty = 1 + 15 + 4 × 1 = 20 bus cycles ± Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle ± Bits in a DRAM are organized as a rectangular array ² DRAM accesses an entire row Advanced DRAM Organization ² Burst mode: supply successive words from a row with reduced latency ± Double data rate (DDR) DRAM ² Transfer on rising and falling clock edges ± Quad data rate (QDR) DRAM Separate DDR inputs and outputs CS/ECE 3330 – Fall 2009 ² 26
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 DRAM Generations 300 Year Capacity $/GB 1980 64Kbit $1500000 100 150 200 250 Trac Tcac 1983 256Kbit $500000 1985 1Mbit $200000 1989 4Mbit $50000 1992 16Mbit $15000 1996 64Mbit $10000
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/04/2009 for the course CS 333 taught by Professor Stankovic during the Fall '08 term at UVA.

Page1 / 12

cs3330-chap5-memory-2 - Example: Intrinsity FastMATH...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online