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ECE230-FS09-SYLLABUS

# ECE230-FS09-SYLLABUS - ECE230 Digital Logic Fundamentals...

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ECE230: Digital Logic Fundamentals 2009 Fall Syllabus Instructor: Dr. Jian Ren O ce: 2211 Engineering Building Phone: 353-4379 Email: [email protected] Website: https://angle.msu.edu Class Hours: MWF: 9:10am-10:00am Classroom: 1145 Engineering Building O ce Hours: MW: 1:30pm-3:00pm or by appointment 1 Required Text Brown, Vransic. \Fundamentals of Digital Logic with VHDL Design," Third Edition, McGraw- Hill, 2009. Available at http://catalogs.mhhe.com/mhhe/viewProductDetails.do?isbn= 0077221435 . * A copy of the course textbook should be on reserve in the Engineering Library. 2 Suggested Text 1. Marcovitz, \Introduction to Logic Design," McGraw-Hill, 2002. ISBN: 0-07-247699-0. 2. Katz, \Contemporary Logic Design," Benjaminn n Cummings Publishing Company, 1994. ISBN: 0-8053-2703-7. 3. Perry, \VHDL Programming by Example," McGraw-Hill, 2002. ISBN: 0-07-140070-2. 3 Course Outline Chapter 5: Number Representation and Arithmetic Circuits Chapter 2: Introduction to Logic Circuits Chapter 4: Optimized Implementation of Logic Functions Chapter 6: Combinational Circuits Building Blocks Chapter 7: Flip-Flops, Registers and Counters Chapter 8: Synchronous Sequential Circuits Chapter 9: Asynchronous Sequential Circuits 4 Grading Policy There will be 3 50-minute exams, 5 projects (4 individual, 1 group), and various homework assign- ments. The exams will be returned in class and then re-collected. Homeworks and projects you can keep.

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ECE230-FS09-SYLLABUS - ECE230 Digital Logic Fundamentals...

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