{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

VHDL_Basics - VHDL VHDL Basics 1 Overview Operators...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
10/12/2009 1 VHDL VHDL Basics 1 Overview Operators Identifiers Data Types Objects Major Constructs Entity Declarations Architecture Body Structural Behavioral (Dataflow) Behavioral (Sequential) Subprograms Packages Use clauses Libraries 2
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
10/12/2009 2 VHDL Operators In order of precedence: Misc.: ** (exponential), ABS, NOT Multiplying: *, /, MOD, REM Sign: +, - Adding: +, -, & (concatenation) Relational: =, /=, <, <=, >, >= Logical: AND, OR, NAND, NOR, XOR, XNOR *There is no precedence among each category. 3 Identifiers Every character is a letter (case not important), digit, or underscore. First character must be a letter No adjacent underscores, can‟t end with an underscore. Can‟t use „reserved words‟, e.g. begin, end, entity. See the following link: http://www.csee.umbc.edu/help/VHDL/reserved. html 4
Image of page 2
10/12/2009 3 Data Types Types STD_LOGIC and STD_LOGIC_VECTOR STD_ULOGIC SIGNED and UNSIGNED INTEGER BOOLEAN ENUMERATION CONSTANT VARIABLE 5 Data Types C <= “1010”; Assigns C(1)=0, C(2)=1, C(3)=0, C(4)=1 Byte <= “10011000”; Assigns Byte(7)=1, Byte(6)=0, … , Byte(0)=0 6
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
10/12/2009 4 Data Types “lowest index TO highest index” “highest index DOWNTO lowest index” Useful for multi-bit signal that is just an array of bits Useful for binary numbers 7 Data Types STD_LOGIC and STD_LOGIC_VECTOR Added to VHDL standard. More flexible than type BIT and BIT_VECTOR Access provided with following statements: LIBRARY ieee; USE ieee.std_logic_1164.all; 8
Image of page 4
10/12/2009 5 Data Types STD_LOGIC and STD_LOGIC_VECTOR Legal values: 0, 1, Z, -; L, H, U, X, and W Only first 4 are useful for synthesis Z is high impedance; - is “don‟t care” L is “weak 0”, H is “weak 1” U is “unitialized”, X is “unknown” W is “weak unknown” 9 Data Types STD_LOGIC and STD_LOGIC_VECTOR SIGNAL x1,x2,Cin,Cout,Sel : STD_LOGIC ; SIGNAL C : STD_LOGIC_VECTOR (1 TO 4); SIGNAL X,Y,S : STD_LOGIC_VECTOR (3 DOWNTO 0); 10
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
10/12/2009 6 Objects Three classes of objects: Signals Variables
Image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern