VHDL_Basics - 1 VHDL VHDL Basics 1 Overview • Operators...

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Unformatted text preview: 10/12/2009 1 VHDL VHDL Basics 1 Overview • Operators • Identifiers • Data Types • Objects • Major Constructs • Entity Declarations • Architecture Body • Structural • Behavioral (Dataflow) • Behavioral (Sequential) • Subprograms • Packages – Use clauses • Libraries 2 10/12/2009 2 VHDL Operators • In order of precedence: – Misc.: ** (exponential), ABS, NOT – Multiplying: *, /, MOD, REM – Sign: +, - – Adding: +, -, & (concatenation) – Relational: =, /=, <, <=, >, >= – Logical: AND, OR, NAND, NOR, XOR, XNOR *There is no precedence among each category. 3 Identifiers • Every character is a letter (case not important), digit, or underscore. • First character must be a letter • No adjacent underscores, can‟t end with an underscore. • Can‟t use „reserved words‟, e.g. begin, end, entity. See the following link: – http://www.csee.umbc.edu/help/VHDL/reserved. html 4 10/12/2009 3 Data Types • Types – STD_LOGIC and STD_LOGIC_VECTOR – STD_ULOGIC – SIGNED and UNSIGNED – INTEGER – BOOLEAN – ENUMERATION – CONSTANT – VARIABLE 5 Data Types • C <= “1010”; – Assigns C(1)=0, C(2)=1, C(3)=0, C(4)=1 • Byte <= “10011000”; – Assigns Byte(7)=1, Byte(6)=0, … , Byte(0)=0 6 10/12/2009 4 Data Types • “lowest index TO highest index” • “highest index DOWNTO lowest index” – Useful for multi-bit signal that is just an array of bits – Useful for binary numbers 7 Data Types • STD_LOGIC and STD_LOGIC_VECTOR – Added to VHDL standard. More flexible than type BIT and BIT_VECTOR – Access provided with following statements: LIBRARY ieee; USE ieee.std_logic_1164.all; 8 10/12/2009 5 Data Types • STD_LOGIC and STD_LOGIC_VECTOR – Legal values: 0, 1, Z, -; L, H, U, X, and W – Only first 4 are useful for synthesis – Z is high impedance; - is “don‟t care” – L is “weak 0”, H is “weak 1” – U is “unitialized”, X is “unknown” – W is “weak unknown” 9 Data Types • STD_LOGIC and STD_LOGIC_VECTOR SIGNAL x1,x2,Cin,Cout,Sel : STD_LOGIC ; SIGNAL C : STD_LOGIC_VECTOR (1 TO 4); SIGNAL X,Y,S : STD_LOGIC_VECTOR (3 DOWNTO 0); 10 10/12/2009 6...
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This note was uploaded on 11/04/2009 for the course ECE 230 taught by Professor Ren during the Spring '08 term at Michigan State University.

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VHDL_Basics - 1 VHDL VHDL Basics 1 Overview • Operators...

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