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ee101_hw4 - EE 101 Homework 4 Fall 09 Redekopp Name Due...

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1 EE 101 Homework 4 Fall ’0 9 ● Redekopp Name: _________________________________________ Lecture 9:30 / 12:30 / 2:00 Due: Tues. Oct 13 th in class Score: ________ Show work to get full credit. Remember, use on only one side of the paper and staple them together. Only use a calculator to CHECK your work, not to DO your work. 1. ( 24 pts.) Design (create one schematic drawing for) each of the following single or multiple output logic functions using the building blocks listed below for each problem along with a NAND gate for each output bit. Hint 1 : In each case you will need to cascade multiple decoders to build a 4-to-16 decoder. Then implement the outputs using that 4-to-16 decoder. Hint 2 : When using a decoder with multiple enables, remember that all enables must be at their active value for the decoder to be enabled. If any enable input is inactive, then the decoder is disabled. a. F 1 = WXYZ (0,3,6,7,10,12,14) (20 pts.) F 0 = WXYZ (1,4,7,13,15) Using (2) 3-to-8 decoders each w/ active-low outputs and 2 enables: 1 active high enable (G1) and 1 active-low (/G2). Besides the 3-to-8 decoders and the NAND gates to implement each output bit, you should not need any additional gates. Note: F1 and F0 are functions of the same inputs, so only 1 decoder can be used but 2 NAND gates are required. b. G = Π ABCD (1,2,5,6,7,9,10,13,14,15) (10 pts.) Using (5) 2-to-4 decoder each w/ (1) active-low enable and active-low outputs 2) (11 pts.) Examine the decoder on the attached page: Label the enable with E or /E depending on whether it is active high or low.
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