EE101Lecture5

# EE101Lecture5 - Lecture 5 Slides Canonical Sums and...

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© Mark Redekopp, All rights reserved Single Variable Theorem (T1) X+0 = X (T1) X •1 = X (T1‟) X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 OR AND Whenever a variable is OR‟ed with 0, the output will be the same as the variable… “0 OR Anything equals that anything” Whenever a variable is AND‟ed with 1, the output will be the same as the variable… “1 AND Anything equals that anything” Hold Y constant
© Mark Redekopp, All rights reserved Single Variable Theorem (T2) X+1 = 1 (T2) X •0 = 0 (T2‟) X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 OR AND Whenever a variable is OR‟ed with 1, the output will be 1… “1 OR anything equals 1” Whenever a variable is AND‟ed with 0, the output will be 0… “0 AND anything equals 0” Hold Y constant

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© Mark Redekopp, All rights reserved Application: Channel Selector Given 4 input, digital music/sound channels and 4 output channels • Given individual “select” inputs that select 1 input channel to be routed to 1 output channel Channel Selector ICH0 ICH1 ICH2 ICH3 OCH0 OCH1 OCH2 OCH3 ISEL0 ISEL1 ISEL2 ISEL3 OSEL0 OSEL1 OSEL2 OSEL3 4 Input channels 4 Output channels Input Channel Select Output Channel Select 011010101001101 101010110101010 101001010101111 001010101001011
© Mark Redekopp, All rights reserved Application: Steering Logic 4-input music channels (ICHx) Select one input channel (use ISELx inputs) Route to one output channel (use OSELx inputs) 011010101001101 101010110101010 101001010101111 001010101001011 ICH0 ICH1 ICH2 ICH3 IS E L0 L1 L2 L3 OSEL0 OSEL1 OSEL2 OSEL3 OCH 0 OCH 1 OCH 2 OCH 3

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© Mark Redekopp, All rights reserved Application: Steering Logic 1 st Level of AND gates act as barriers only passing 1 channel OR gates combines 3 streams of 0‟s with the 1 channel that got passed (i.e. ICH1) 2 nd Level of AND gates passes the channel to only the selected output ICH0 ICH1 ICH2 ICH3 I SEL0 SEL1 SEL2 SEL3 OSEL0 O SE L1 OSEL2 OSEL3 OCH 0 OCH 1 OCH 2 OCH 3 0 0 0 1 0 0 0 1 0 0 0 ICH1 ICH1 1 0 0 0 ICH1 ICH1 ICH1 ICH1 ICH1 0 0 0 0 1 0 0 OR: 0 + ICH1 + 0 + 0 = ICH1 AND: 1 AND ICH1 = ICH1 0 AND ICH1 = 0 AND: 1 AND ICHx = ICHx 0 AND ICHx = 0 Connection Point
© Mark Redekopp, All rights reserved Logic Functions A logic function maps input combinations to an output value („1‟ or „0‟) 3 possible representations of a function Equation Schematic Truth Table Can convert between representations Truth table is only unique representation

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© Mark Redekopp, All rights reserved Checkers / Decoders An AND gate only outputs „1‟ for 1 combination That combination can be changed by adding inverters to the inputs – We can think of the AND gate as “checking” or “decoding” a specific combination and outputting a „1‟ when it matches.
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## This note was uploaded on 11/08/2009 for the course EE 101 at USC.

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EE101Lecture5 - Lecture 5 Slides Canonical Sums and...

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