{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

EE101Lecture9

# EE101Lecture9 - Introduction to Digital Logic Lecture 9...

This preview shows pages 1–9. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
© Mark Redekopp, All rights reserved Logic Function Synthesis Given a function description as a T.T. or canonical form, how can we arrive at a circuit implementation or equation (i.e. perform logic synthesis)? 5 methods to be discussed Canonical sum/product + Simplification w/ theorems Karnaugh Maps Decoders + 1 gate per output Multiplexers Memories (used as Look-Up- Tables [LUT‟s])
© Mark Redekopp, All rights reserved Decoders A decoder is a building block that: Takes in an n-bit binary number as input Decodes that binary number and activates the corresponding output Individual outputs for EVERY input combination (i.e. 2 n outputs) D0 D1 D2 D3 D4 D5 D6 D7 X (MSB) Y Z (LSB) 1 output for each combination of the input number 3-bit binary number 3-to-8 Decoder

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
© Mark Redekopp, All rights reserved Decoders A decoder is a building block that: Takes a binary number as input Decodes that binary number and activates the corresponding output Put in 6=110, Output 6 activates („1‟) Put in 5=101, Output 5 activates („1‟) D0 D1 D2 D3 D4 D5 D6 D7 X (MSB) Y Z (LSB) 0 1 1 0 0 0 0 0 0 1 0 Binary #6 Only that numbered output is activated
© Mark Redekopp, All rights reserved Decoders A decoder is a building block that: Takes a binary number as input Decodes that binary number and activates the corresponding output Put in 6=110, Output 6 activates („1‟) Put in 5=101, Output 5 activates („1‟) D0 D1 D2 D3 D4 D5 D6 D7 X (MSB) Y Z (LSB) 1 0 1 0 0 0 0 0 1 0 0 Binary #5 Only that numbered output is activated

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
© Mark Redekopp, All rights reserved Decoder Sizes A decoder w/ an n-bit input bit input has 2 n outputs 1 output for every combination of the n-bit input Y X D0 D1 D2 D3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A2 A1 A0 2-to-4 Decoder 3-to-8 Decoder 0 1 1 0 0 0 n inputs (2) 2 n inputs (4) n inputs (3) 2 n inputs (8) 0 0 0 1 0 0 0 0 0 0 0 (MSB) (MSB) (MSB)
© Mark Redekopp, All rights reserved Building Decoders Checker for 000 Checker for 001 Checker for 010 Checker for 011 Checker for 100 Checker for 101 Checker for 110 Checker for 111 3-bit number [A2:A0] O0 O1 O2 O3 O4 O5 O6 O7

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
© Mark Redekopp, All rights reserved Building Decoders Y X D0 D1 D2 D3 D0 = X‟•Y‟ X Y D0 D1 D2 D3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 x y D0 x y
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}