EE101Lecture17

EE101Lecture17 - Introduction to Digital Logic Lecture 17:...

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© Mark Redekopp, All rights reserved Introduction to Digital Logic Lecture 17: Latches Flip-Flops
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© Mark Redekopp, All rights reserved Problem w/ Bistables Output should have been 0 at end of sequence Problem: Glitch was remembered Need some way to ignore inputs until they are stable and valid 0 Glitch causes Q to be set X O A>B Q 2 6 7 R S Q Q O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B X 10 0 0 1
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© Mark Redekopp, All rights reserved Latches Latches are bistables that include a new clock input (sometimes called the ‘gate’ or ‘enable’) The clock input will tell the latch when to ignore the inputs (when C=0) and when to respond to them (when C=1) RS Bistable RS Latch R S Q Q C R Internal S Internal
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© Mark Redekopp, All rights reserved Latches RS Latch (C=0) 0 RS Latch (C=1) 0 0 Q Q C=0 causes S=R=0 and thus Q and Q remain unchanged C=1 allows S,R to pass and thus Q and Q are set, reset or remain unchanged based on those inputs 1 R S R S Q Q C R S Q Q C
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© Mark Redekopp, All rights reserved Clock Signals A clock signal is an alternating sequence of 1’s and 0’s It can be used to help ignore the inputs of a bistable when there might be glitches or other invalid values Idea: When clock is 0, ignore inputs When clock is 1, respond to inputs Sample Clock Signal 0 1 0 1 0 1 0 1 0 1 0 1 t = 0 ms 1 ms 2 ms 3 ms 4 ms 5 ms f = 1/T = 1 kHz
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© Mark Redekopp, All rights reserved Solution with Latches C = 0 when inputs change In fact, in a real digital system, it is C’s transition to 0 that triggers the inputs to change Glitches occur during this time and are filtered When C = 1, inputs are stable and no glitches will occur Glitch gets filtered in latch because C=0
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© Mark Redekopp, All rights reserved Latches Rule – When clock = 0, inputs don’t matter, outputs remain the same When clock = 1, inputs pass to the inner bistable and the outputs change based on those inputs
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© Mark Redekopp, All rights reserved SR-Latch When C = 0, Q holds (remembers) its value When C = 1, Q responds as a normal SR- bistable CLK S R Q Q 0 x x Q 0 Q 0 1 0 0 Q 0 Q 0 1 1 0 1 0 1 0 1 0 1 1 1 1 illegal R S C Q Q’
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© Mark Redekopp, All rights reserved SR-Latch CLK S R Q Q 0 x x Q 0 Q 0 1 0 0 Q 0 Q 0 1 1 0 1 0 1 0 1 0 1 1 1 1 illegal S=1,R=0 causes Q=1 S=0,R=1 causes Q=0 S=1,R=0 causes Q=1 When C=0, Q holds its value R S C Q Q’ CLK Q S R
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© Mark Redekopp, All rights reserved RS (SR) Latches C S R Q Q 0 x x Q 0 Q 0 1 0 0 Q 0 Q 0 1 1 0 1 0 1 0 1 0 1 1 1 1 illegal illegal When C=0, outputs don’t change no matter what the inputs do When C=1, outputs change based on inputs S R Q Q CLK R S C Q Q’ SR Latch
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© Mark Redekopp, All rights reserved RS (SR) Latches C S R Q Q 0 x x Q 0 Q 0 1 0 0 Q 0 Q 0 1 1 0 1 0 1 0 1 0 1 1 1 1 illegal illegal When C=0, ignore inputs When C=1, outputs change based on inputs S R Q Q CLK R S C Q Q’ SR Latch
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© Mark Redekopp, All rights reserved Adding a Sequence of Numbers Back to our example of adding a sequence of numbers
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