EE101Lecture25

EE101Lecture25 - Introduction to Digital Logic Lecture 25...

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© Mark Redekopp, All rights reserved Introduction to Digital Logic Lecture 25 Simple CPU Overview Instruction Set
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© Mark Redekopp, All rights reserved Software Process Software Program High Level Language Description Assembly (.asm/.s files) Executable Binary Image if (x > 0) x = x + y - z; a = b*x; JLEZ X,SKIP ADD X,X,Y SUB X,X,Z SKIP: MUL A,B,X 1110 0010 0101 1001 0110 1011 0000 1100 0100 1101 0111 1111 1010 1100 0010 1011 0001 0110 0011 1000 .c/.cpp files 1110 0010 0101 1001 0110 1011 0000 1100 0100 1101 0111 1111 1010 1100 0010 1011 0001 0110 0011 1000 Object/Machine Code (.o files) Compiler Assembler Linker Loader / OS Program Executing A “compiler” (i.e. gcc, VisualC++, etc.) also includes the assembler & linker
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© Mark Redekopp, All rights reserved Hardware Components Computer hardware can be classified into three categories Input/Output Devices Supplies and consumes data Supplies the program Keyboard, Mouse, Monitor, Hard Drive Memory (RAM/ROM) Temporary storage for data and program Processor Performs operations on data as indicated by SW program Pentium, Celeron, etc. Processor Memory Output Devices Input Devices Software Program Data
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© Mark Redekopp, All rights reserved Memory Like the memories we learned about earlier Set of cells/rows that each store a group of bits (usually, 1 byte = 8 bits) but can be larger like 2-bytes = 16-bits, or even 4-bytes = 32-bits, etc. Unique address assigned to each cell/row Used to reference the value in that location 11010010 01001011 10010000 11110100 01101000 11010001 00001011 0 1 2 3 4 5 FF 16 Address Data Memory Device
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© Mark Redekopp, All rights reserved Memory Operations Memories perform 2 operations Read: retrieves data value in a particular location (specified using the address) Write: changes data in a location to a new value To perform these operations a set of address , data , and control inputs/outputs are used Note: A group of wires/signals is referred to as a „bus‟ Thus, we say that memories have an address , data , and control bus bus . 11010010 01001011 10010000 11110100 01101000 11010001 00001011 0 1 2 3 4 5 1023 11010010 01001011 10010000 11110100 01101000 00000110 00001011 0 1 2 3 4 5 1023 2 10010000 Read Addr. Data Control Addr. Data Control 5 00000110 Write A Write Operation A Read Operation
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© Mark Redekopp, All rights reserved Processor Performs the same 3-step process over and over again Fetch an instruction from memory Decode/Control the instruction Generate necessary control signals to control the datapath to execute the given instruction Execute the instruction Perform the specified operation These 3 steps are known as the Instruction Cycle Processor Memory ADD SUB CMP Arithmetic Circuitry Control Circuitry 1 Fetch Instruction Generate control signals Add the specified values 2 3 Address Data Control
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© Mark Redekopp, All rights reserved Processor 3 Primary Components of a Processor ALU Registers Control Circuitry Connects to memory and I/O via address, data, and control buses Processor Addr Data Control Memory 0 1 2 3 4 5 6
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This note was uploaded on 11/08/2009 for the course EE 101 at USC.

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EE101Lecture25 - Introduction to Digital Logic Lecture 25...

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