ho32.l29_techno.wrapup

ho32.l29_techno.wrapup - Lecture 29 Technology Scaling...

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1 Lecture 29 Technology Scaling– Beyond EE114 MOSFETs R. Dutton, B. Murmann Stanford University R. Dutton, B. Murmann 1 EE114 (HO #32) MOS Level 1 Figures-of-Merit (FoM) Long Channel Model Current Efficiency D m I g OV V 2 = I DS = KP 2 W L V GS V t ( ) 2 1 + λ V DS ( ) ds m g g Transit Frequency Intrinsic Gain 2 OV L V 2 3 μ = gs m C g OV V 2 •Simplicity of Level 1 has allowed nea -perfect accuracy eff V t = V TO + γ 2 φ V BS 2 () R. Dutton, B. Murmann 2 Simplicity of has allowed near perfect accuracy in having hand-calculations and SPICE-simulations agree •What are the trends in state-of-the-art MOS technology? •What modeling and methodology is needed for advanced MOS devices? EE114 (HO #32)
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2 Trends in Scaling Different “flavors” of Transistors: Core Digital, I/O, Special I ds ?? g m /g ds BSIM Devices R. Dutton, B. Murmann 3 1.8V 3.3V STI D rain- E xtended (we’ll come back to special devices) Two Problems : •Decrease in intrinsic gain •Bias dependent EE114 (HO #32) Dependence on V DS The long channel model predicts that g ds and g m /g ds are independent of V DS – As long as device is biased in active region This is also no longer true in modern devices –g ds (and therefore g m /g ds ) shows a significant dependence on V DS I D Slope = g ds1 OP2 Slope = g ds2 R. Dutton, B. Murmann 4 V DS OP1 Physical effects beyond “channel length modulation” critical EE114 (HO #32)
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3 Observations – Intrinsic Gain •g m/ g ds shows a strong dependence on V DS bias – Mostly due to varying g ds There is a gradual transition from triode to active – Long channel model would have predicted an abrupt change to large intrinsic gain at V DS = V OV – Typically need V DS > V OV + 4kT/q to ensure at least moderate intrinsic gain At high V DS , g ds increases due to SCBE (substrate current induced body-effect); this causes a decrease in g m /g ds R. Dutton, B. Murmann 5 – Highly technology dependent, and usually not present in PMOS devices – If you are interested in more details, please refer to EE316 or a similar course EE114 (HO #32) The Good News •Large improvements in f T •Product of g m /I d times f T R. Dutton, B. Murmann 6 is becoming sharper; closer to the sub- threshold region EE114 (HO #32)
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4 MOS R&D Prototypes vs. Production Versions R&D Prototype Technology: Non-classical structures, physics limited, drastic variations, and higher cost 30nm 20nm 15nm 10nm 7nm 5nm (2000) (2001) (2001) (2003) (2005) (?) Plane BOX (<20nm) Bulk wafer FD Si film Source: Intel, ITRS R. Dutton, B. Murmann 7 Production Prototypes: Power- and robustness-constrained, adaptive, billion-scale integration, gigaHz operation 65nm (2005) 45nm (2007) 32nm (2009) 22nm (2011) 16nm (2013) 11nm (2015) EE114 (HO #32) Example--45 nm Technology Node 1E-4 1E-3 0.01 Fujitsu 45nm node L eff =25nm (N) 35nm(P) 1V 0.05V Data PTM 600 700 800 900 0.85V 1V Fujitsu 45nm node L eff =25nm (N) 35nm (P) Data PTM -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
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ho32.l29_techno.wrapup - Lecture 29 Technology Scaling...

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