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Unformatted text preview: EE114 Autumn 08/09 R. Dutton, B. Murmann Page 1 of 2 Last modified 10/10/2008 11:43:00 AM HOMEWORK #3 (Due: Friday, October 17, 2008, noon PT) 1. Consider the circuit on slides 19/20 of lecture 6. With = 0.1 V-1 , the quiescent point output voltage (V O ) is set exactly at 2.5V. Compute V O for the two cases when changes by +50% and -50%, respectively. As mentioned in class, such discrepancies may be due to variations in the semiconductor process or simply due to uncertainty in the simplistic model used to incorporate finite dI D /dV ds . 2. Assume that you have just joined a new company and that their technology and technology files for SPICE are quite different from what you have worked with at your previous company. Hence, you need to do some hand calculations and related SPICE simulations to confirm what you can expect with the technology at hand. Here is how you will go about the task: a) Assume a W=30 m and L=1.6 m NMOS device, with KP=50 A/V 2 , VTO=0.5V and COX=2.3mF/m 2 (using the Lambda scaling rule given in Lect. 5, p. 18); for a bias current of 0.25mA and assumed Vds=2.5V, compute (by hand) the required Vgs and resulting Cgs and small-signal gm and gds (ignoring all extrinsic capacitances). b) Construct an HSPICE deck, similar to that shown in Lect. 6, p. 21 but only to be used for the dc operating point and .op output. This time use R=5K and R i =10K...
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This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.