EE114_HW4_Solutions

EE114_HW4_Solutions - itest n1 0 ac 1.op.ac 100G.option...

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Q4 d. * Q4 , d , HW4 , ee114 .model my_pmos pmos kp = 25u vto = -0.5 cox = 2.3e-3 capop = 0 v1 v1 0 dc 1 Ri v1 g 1e6 m1 0 g s s my_pmos W = 20u L = 1u Ibias vdd s dc 1e-3 itest s 0 ac 1 vdd vdd 0 5 .op .ac dec 10 100 100G .option post brief nomod .end * simulating the RL equivaleny model for the circuit. R2 n1 0 1e+6 R1 n1 n2 1e+3 L1 n2 0 30.67e-6
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Unformatted text preview: itest n1 0 ac 1 .op .ac dec 10 100 100G .option post brief nomod .end Q4 .e * Q4 , e , HW4 , ee114 .model my_pmos pmos kp = 25u vto = -0.5 cox = 2.3e-3 capop = 0 v1 v1 0 dc 1 pwl 0 1 1ns 2 Ri v1 g 1e6 m1 0 g s s my_pmos W = 20u L = 1u Ibias vdd s dc 1e-3 itest 0 s ac 1 vdd vdd 0 3 Cl s 0 0.5e-12 .op .trans 0.5ns 1u .option post brief nomod .end...
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This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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EE114_HW4_Solutions - itest n1 0 ac 1.op.ac 100G.option...

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