EE114_HW4

EE114_HW4 - EE114 Autumn 08/09 R. Dutton, B. Murmann Page 1...

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EE114 Autumn 08/09 R. Dutton, B. Murmann Page 1 of 3 HOMEWORK #4 (Due: Friday, October 24, 2008, noon PT) 1. Consider the cascode circuit (CS-CG) on slide 24 of lecture 10. For simplicity in this problem assume λ =0 and ignore backgate effect in your calculations. a) Calculate the quiescent point voltage at the source of MNC (V X ), assume V O =V B =2.5V and IB is such that both the devices are in saturation. b) Compute all intrinsic and extrinsic device capacitances of MN1 and MNC. For the calculation of junction capacitances, use your result from part (a) and assume V O =V B =2.5V. (Use the parameters values(like AS, PB, Cov, Ldiff etc) from HW#3 for extrinsic capacitor calculations) c) Compute the -3dB bandwidth of this circuit using a ZVTC analysis. How closely does your answer match the simulation result on slide 25? State the percent error. d) Compare the symbolic expression for the time constant associated with C gd of MN1 in this circuit with the expression on slide 10 of lecture 9. Explain qualitatively why the cascode helps improve the -3dB bandwidth in this circuit. 2. In this problem, we will investigate an interesting case in which the benefit of cascoding is dependent upon operating frequency. In the cascoded common source stage shown in Figure 1 all devices are biased in the saturation region. You may neglect backgate effect, but you
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This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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EE114_HW4 - EE114 Autumn 08/09 R. Dutton, B. Murmann Page 1...

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