EE114_HW6_updated

# EE114_HW6_updated - EE114 Autumn 08/09 R. Dutton, B....

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EE114 Autumn 08/09 R. Dutton, B. Murmann Page 1 of 5 Last modified 11/22/2008 3:03:00 PM HOMEWORK #6 (Due: Friday, December 5, 2008, noon PT) Please refer to EE114 technology device parameters from lecture 7 slide 12 whenever you need device constants in your calculations. 1) Consider the Wilson current source circuit shown below. Neglect backgate effect and all capacitances. Neglect channel length modulation in bias point calculations, but be sure to include finite r o in your small-signal analyses. a) Calculate the return ratio (RR) of M3. b) Calculate the output resistance R o at node V o using Blackman’s formula.

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EE114 Autumn 08/09 R. Dutton, B. Murmann Page 2 of 5 Last modified 11/22/2008 3:03:00 PM 2) The figure below shows a bias generator used in an integrated circuit (startup circuit not shown). In order to test the circuit and externally modify the bias current, the chip designer made the node V x “off-chip accessible” by connecting it to one of the device pins. Due this connection, there are now parasitic capacitances present at node V x . All these parasitic have been lumped into capacitor C x as shown in the figure. In your analysis of this circuit, neglect channel length modulation, backgate effect, extrinsic and intrinsic device capacitances unless otherwise stated. Important note: The circuit examined in this problem has a positive feedback loop. A circuit with positive feedback is unstable unless the magnitude of its loop gain is less than 1 over all frequencies . a)
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## This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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EE114_HW6_updated - EE114 Autumn 08/09 R. Dutton, B....

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