ho10.l07_extrinsic_cap

ho10.l07_extrinsic_cap - Lecture 7 Extrinsic Capacitance R....

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1 Lecture 7 Extrinsic Capacitance R. Dutton, B. Murmann R. Dutton, B. Murmann 1 EE114 (HO #10) Stanford University Extrinsic Capacitance C jdb C jsb C ov C ov R. Dutton, B. Murmann 2 EE114 (HO #10) Overlap capacitance – Gate to source and gate to drain Junction capacitance – Source to bulk and drain to bulk
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2 Overlap Capacitance Two components – Direct overlap ~ C WL l Direct overlap C ox overlap – Additional component due to fringing field • Non-negligible in modern technology (gate thickness is large compared to other feature sizes) Simple model equation C ov = C ov ' · W EE114 technology: – C ov '= 0.5fF/ μ m for both NMOS and PMOS R. Dutton, B. Murmann 3 EE114 (HO #10) – Spice model parameters: CGSO=0.5n, CGDO=0.5n Junction Capacitance (1) Two components: – Area (AS, AD) and Perimeter (PS, PD) capacitance L L L diff diff G SD W AS = W L diff PS = W + 2L diff AD = W L diff PD = W + 2L diff R. Dutton, B. Murmann 4 EE114 (HO #10) EE114 technology: L diff = 3 μ m
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3 Junction Capacitance (2) MJSW DB MJ DB jdb V CJSW PD V CJ AD C + + + = 1 1 MJSW SB MJ SB jsb V CJSW PS V CJ AS C + + + = 1 1 PB PB EE114 Technology CJ CJSW MJ MJSW PB NMOS 0.1 fF/ μ m 2 0.5 fF/ μ m 0.5 0.33 0.95V PB PB R. Dutton, B. Murmann 5 EE114 (HO #10) PMOS 0.1 fF/ μ m 2 0.35 fF/ μ m 0.5 0.33 0.95V Junction Capacitance in Spice (1) There are two ways to handle junction capacitance in Spice The first one is to compute AS, AD, PS, PD manually for each MOSFET (tedious…) *** netlist *...
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This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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ho10.l07_extrinsic_cap - Lecture 7 Extrinsic Capacitance R....

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