ho13.l10_cg

ho13.l10_cg - Lecture 10 Backgate Effect Common Gate Stage...

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1 Lecture 10 Backgate Effect Common Gate Stage R. Dutton, B. Murmann R. Dutton, B. Murmann 1 EE114 (HO #13) Stanford University The "Atoms" of Analog Circuit Design As we've seen from the discussion so far, a common source stage is sufficient for building a simple amplifier – How about the other two possible configurations? We'll find that common gate and drain stages can be R. Dutton, B. Murmann 2 EE114 (HO #13) incorporated as valuable add-ons, for building "better" amplifiers Interestingly, many analog circuits can be decomposed into a combination of the above three fundamental building blocks
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2 Bulk Connection * Be aware : •Ask the tech. folks •Know what it means! R. Dutton, B. Murmann 3 EE114 (HO #13) In the EE114 (N-well) technology, only the PMOS device has an isolated bulk connection Newer technologies * (e.g. 0.13 μ m CMOS) also tend to have NMOS devices with isolated bulk ("tripple-well" process) Aside: Modern Triple-Well Process Courtesy Shoichi Masui n+ p+ p+ R. Dutton, B. Murmann 4 EE114 (HO #13)
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3 Bulk Connection Scenarios V DD NMOS R. Dutton, B. Murmann 5 EE114 (HO #13) Can connect bulk to source or V DD PMOS PMOS Well Capacitance In the EE114 (N-well) technology, the PMOS transistor is a 5 terminal device – G, D, S, B, Substrate N-well forms a PN junction with the substrate – Often "AC shorted" when N-well=V DD , Substrate=GND – Not shorted when we connect N-well to source! • Resulting capacitance ~ 0.05 fF/ μ m 2 • Not modeled in Spice! Must add extra diode manually in this case R. Dutton, B. Murmann 6 EE114 (HO #13)
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4 Model for PMOS Well Capacitance Model available in ee114_hspice.sp * well-to-substrate diode * example instantiation (area = 10um*10um = 100pm^2) * (anode) (cathode) (model) (area) * d1 sub_node well_node dwell 100p model dwell d cj0=1e- 4m= 05 R. Dutton, B. Murmann 7 .model dwell d cj0 1e 4 m0.5 EE114 (HO #13) Well Area Estimation Highly dependent on exact layout For the e ample on LL diff L diff
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This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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ho13.l10_cg - Lecture 10 Backgate Effect Common Gate Stage...

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