ho15.l12_proc_var

ho15.l12_proc_var - Lecture 12 PVT Variations Device...

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1 Lecture 12 PVT Variations Device Mismatch R. Dutton, B. Murmann R. Dutton, B. Murmann 1 EE114 (HO # 15) Stanford University Re-cap What we’ve covered so far – Device modeling – Analysis tools (Miller approximation, ZVTC) – Fundamental stage configurations (CS, CG, CD) What we have implicitly assumed – We have nearly ideal current and voltage sources available to set up the transistors’ bias points – Transistor parameters and supply voltage do not vary The next set of lectures will move us toward the practical R. Dutton, B. Murmann 2 implementation of transistor stages – Focusing on biasing schemes that are insensitive to variations commonly seen in IC technology EE114 (HO # 15)
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2 Overview P rocess, V oltage and T emperature Variations, Device mismatch (Lecture 12) I ref V DD V DD V BIAS1 Supply Independent Bias Circuit V DD Lecture 14 Biasing R. Dutton, B. Murmann 3 EE114 (HO # 15) V BIAS2 Current Mirrors Lecture 13 Considerations Lecture 15 PVT Variations PROCESS – Variations between production lots – "Slow, Nominal and Fast" corners VOLTAGE –V DD is usually specified only within ± 10% – E.g. V DD = 4.5…5.5 V for our technology TEMPERATURE – Ambient temperature variations R. Dutton, B. Murmann 4 EE114 (HO # 15) – 0…70°C (or -40…125°C)
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3 Process Variations Wafer made yesterday All NMOS are “slow” All PMOS are “nominal” All R are nomina Wafer made today All NMOS are “fast” All PMOS are “fast” All R are nomina Parameter “Slow” “Nominal” “Fast”
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ho15.l12_proc_var - Lecture 12 PVT Variations Device...

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