ho16.l13_mirrors

# ho16.l13_mirrors - Current Mirrors R Dutton B Murmann...

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1 Lecture 13 Current Mirrors R. Dutton, B. Murmann Stanford University B. Murmann 1 EE114 (HO #16) Basic Analysis ( λ =0) I I I O V I V O L W C I V V V ox i t I gs μ + = 2 () 1 2 1 2 1 = μ μ = t GS ox t GS ox I O V V L W C V V L W C I I W/L M 1 W/L M 2 B. Murmann 2 EE114 (HO #16) M1 “computes” gate-source voltage M2 sees same V GS , and therefore I O =I I (to first order) – Note that this result holds even with large variations in V t or μ C ox that are common to M1 and M2

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2 Typical Design Objectives Minimize error in I O Minimize compliance voltage V omin Minimize capacitance C B. Murmann 3 EE114 (HO #16) o Maximize R o Want to be able to scale currents, i.e. I O =K I I Current Scaling (1) The abo e eq ation s ggests that e can set K b scaling ( ) () K V V L W C V V L W C I I ! t GS ox t GS ox I O = μ μ = 1 1 2 2 2 1 2 1 B. Murmann 4 EE114 (HO #16) The above equation suggests that we can set K by scaling either or both the widths and lengths of the two MOSFETS – This deserves a closer look
3 Current Scaling (2) The solid curve to the right shows how the current of a modern MOSFET 450 NMOS I D vs. 1/L in 90-nm technology. V GS =V DS =500mV (V t ~300mV) a modern MOSFET changes with 1/L Very different from our long channel model, which predicts I D 1/L Bottom line – Impossible to make 100 150 200 250 300 350 400 I D [ μ A] long channel model real device B. Murmann 5 current mirrors with reasonable accuracy unless L 1 =L 2 EE114 (HO #16) 0 2 4 6 8 10 12 14 0 50 1/L [ μ m -1 ] Current Scaling (3) The remaining (and only option) for scaling the current is to use devices with different widths •B a s i c possibility from a layout perspective (e.g. K=2)

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## This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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ho16.l13_mirrors - Current Mirrors R Dutton B Murmann...

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