ho21.l18_multi_stage

# ho21.l18_multi_stage - Lecture 18 18 Multi-Stage Amplifiers...

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1 Lecture 18 Multi-Stage Amplifiers (Differential Stages) R. Dutton, B. Murmann R. Dutton, B. Murmann 1 EE114 (HO #21) Stanford University Single-Ended Cascading Problems Output quiescent point voltage (V DS ) is equal to input quiescent point (V GS ) V V V – Usually not a good choice – Want V DS ~ V DD /2 and V GS ~ V t + a few hundred mV Hard to guarantee a stable operating point – Any error in V B1 (e.g. due t1 0V V it h i I B B3 I B B2 I B B1 R. Dutton, B. Murmann 2 to ~10mV V t mismatch in the bias generator) will be amplified by subsequent stages and may rail the output EE114 (HO #21)

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2 Cascading Differential Amplifiers Does this really work (and why) R. Dutton, B. Murmann 3 Answer : YES, absolutely (and open-loop, without feedback to control node voltages) Why does it work : The current sources demand that drain currents obey; V GS values are then fixed, in turn setting drain voltages EE114 (HO #21) How much gain (and bandwidth) More gain per stage is not always best. Ultimately there is a gain- bandwidth trade-off, limited by the transistor f T . Hence, cascading multiple stages with less gain (and more bandwidth each) is one way to maximize overall gain and bandwidth to maximize overall gain and bandwidth. R L R L R L R L R. Dutton, B. Murmann 4 Let’s look the half-circuit with loading But: there’s no free lunch. In the end you can’t cascade to get more gain and still get bandwidth=f T . Let’s see why… EE114 (HO #21)
3 Cascading (Diff-Pair “in disguise”) v 2 Differential Mode Half Circuit (applicable for full- v o1 Source-Follower-CG--Gain: v in =v id v x o2 differential and cascaded stages) A V _ DM v od v id = − g m 1 R Small-signal model for general analysis (especially if symmetry not imposed) R. Dutton, B. Murmann

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## This note was uploaded on 11/09/2009 for the course EE 114 at Stanford.

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ho21.l18_multi_stage - Lecture 18 18 Multi-Stage Amplifiers...

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