bram_block - 0 Block RAM(BRAM Block(v1.00a DS444 0 0...

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Block RAM (BRAM) Block (v1.00a) DS444 August 13, 2004 0 0 Product Specification DS444 August 13, 2004 www.xilinx.com 1 Product Specification 1-800-255-7778 © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Introduction The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. The BRAM Block structural HDL is generated by the EDK design tools based on the configuration of the BRAM inter- face controller IP. All BRAM Block parameters are automat- ically calculated and assigned by the EDK tools Platgen and Simgen. Features Fully automated generation and configuration of HDL through EDK Platgen/Simgen tools. Number of BRAM primitives utilized is a function of the configuration parameters for: memory address range, number of byte-write enables, the data width, and the targeted architecture Both Port A and Port B of the memory block can be connected to independent BRAM Interface Controllers: LMB (Local Memory Bus), OPB (On-chip Peripheral Bus), PLB (Processor Local Bus), and OCM (On-Chip Memory). Supports byte, half-word, word, and doubleword transfers provided the correct number of byte-write enables have been configured LogiCORE™ Facts Core Specifics Supported Device Family QPro™-R Virtex-II™, QPro Virtex-II, Spartan-II™, Spartan-IIE , Spartan-3™, Virtex , Virtex-II™, Virtex-II Pro™, Virtex-4 , Virtex-E
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