client server setup to send data

client server setup to send data - Application Note: Xilinx...

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XAPP441 (v1.1) September 9, 2006 www.xilinx.com 1 © 2005-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Summary Field upgradeability is one of the key features of recent FPGA based systems. This application note describes techniques for remote FPGA reconfiguration through an Ethernet port. Remote reconfiguration as demonstrated in this document will require the use of either MicroBlaze TM or PowerPC TM embedded processors, external Flash, SDRAM memory, and a Xilinx CPLD. "Watch-dog" monitoring is included in the solution. This application note also presents a system level solution using a Xilinx CPLD and Flash memory to configure and monitor Xilinx FPGA configuration status. Introduction For this application note, Xilinx designed a special daughter card, which can be plugged into a P-160 module connector on an Insight Virtex TM -II Pro development board. But, you can design and build your own system using this application note. The main target of our reference design is Wireless BTS (Base Tranceiver Station), but you can target any other system which requires a remote FPGA reconfiguration solution . RFCS (Remote FPGA Configuration System) System Overview There are five main devices in this system: Target FPGA : The target FPGA is used to implement the main user design. It also incorporates the MicroBlaze or PowerPC processor with GPIO, EMC, UART, EMAC and the SDRAM controller CPLD : The CPLD is used to implement the FPGA reconfiguration, and perform hardware and software configuration watch-dog and status monitoring. This design can use the XC95288XL or the XC2C256 CPLD device. Flash memory : Used to store FPGA hardware and firmware image. It is usually divided into four areas Factory default hardware sector: Used to store known good data and reconfigure the FPGA if the hardware update fails Factory default software sector Hardware update sector. After power up, the CPLD gets the FPGA bit stream data from this sector and tries to configure the FPGA three times. If this fails or results in a software loading timeout, then the CPLD sets the Flash bank address (2-bit MSB) to the factory default area (known good data) and reverts to the previous FPGA configuration Software update sector Ethernet PHY device Application Note: Xilinx FPGA XAPP441 (v1.1) September 9, 2006 Remote FPGA Reconfiguration Using MicroBlaze or PowerPC Processors Author: KY Park and Hyuk Kim R Table 1: Supported Devices MicroBlaze Processor Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan TM -II, Spartan-IIE, Spartan-3 and Spartan-3E PowerPC Processor Virtex-II Pro and Virtex-4 FX
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2 www.xilinx.com XAPP441 (v1.1) September 9, 2006 Introduction R SDRAM device: In this application the memory type used on the board is SDRAM. However, DDR SDRAM, DDR-II SDRAM, SRAM, and other devices can be used as well.
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This note was uploaded on 11/11/2009 for the course CSE CS taught by Professor Crm during the Spring '08 term at Indian Institute of Technology, Kharagpur.

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client server setup to send data - Application Note: Xilinx...

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